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公开(公告)号：US20190386614A1
公开(公告)日：2019-12-19
申请号：US16011793
申请日：2018-06-19
发明人： Grant P. Kesselring , James Strom , Scott Trcka , Ann Chen Wu
摘要： A voltage-controlled oscillator (VCO) having an operating frequency dependent on a total capacitance of selectable tuning capacitors can be fabricated within an integrated circuit (IC). The VCO can include active electronic devices fabricated within a set of lower layers of the IC and selectable tuning capacitors having electrically conductive structures separated by dielectric material fabricated within a set of upper layers of the IC. The upper layers of the IC are located above the set of lower layers of the IC. The VCO can also include a set of interconnect structures configurable to select a total capacitance of the selectable tuning capacitors by electrically interconnecting the first portion of the VCO to capacitors of the at least one selectable tuning capacitor.
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公开(公告)号：US11558057B1
公开(公告)日：2023-01-17
申请号：US17519438
申请日：2021-11-04
摘要： A phase locked loop includes a pulse limiter between a phase frequency detector and a charge pump. The phase frequency detector generates and sends a clock pulse to the pulse limiter. The pulse limiter generates a first signal that indicates that the clock pulse is greater than a minimum pulse width of the phase frequency detector. The pulse limiter receives a pulse limiter buffer selection signal that selects one buffer of a plurality of buffers within the pulse limiter. The pulse limiter generates a second signal that indicates a truncated pulse width as the minimum pulse width of the phase frequency detector plus a delay period that is associated with the pulse limiter buffer selection signal. The pulse limiter truncates the clock pulse to the truncated pulse width and sends the truncated clock pulse to the charge pump.
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公开(公告)号：US11496094B1
公开(公告)日：2022-11-08
申请号：US17239862
申请日：2021-04-26
IPC分类号： H03B5/12
摘要： A voltage-controlled oscillator comprises a varactor. A capacitance of the first varactor is dependent upon a control voltage. The voltage-controlled also comprises an inductor. The inductor is connected to a center-tap connection. The voltage-controlled oscillator also comprises a power source. The power source is configured to provide a bias voltage to the inductor through the center-tap connection. The voltage-controlled oscillator also comprises a coupling capacitor. The coupling capacitor is located between the inductor and the varactor. The voltage-controlled oscillator also comprises a coupling resistor. The coupling resistor is located between the coupling capacitor and the center-tap connection. The center-tap connection provides the bias voltage to the coupling capacitor through the coupling resistor.
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公开(公告)号：US11303285B1
公开(公告)日：2022-04-12
申请号：US17340239
申请日：2021-06-07
摘要： A phase locked loop having a charge pump is described. The charge pump has circuitry to select a mode for each semiconductor chip from a plurality of modes to enhance yield. Nine unique modes are defined from which a selection is made for each chip. The selected mode mitigates effects of device mistracking anomalies for each chip. A method is provided to show how the modes are determined and prioritized.
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公开(公告)号：US20230035405A1
公开(公告)日：2023-02-02
申请号：US17386043
申请日：2021-07-27
发明人： Matthew James Paschal , Daniel M. Dreps , Glen A. Wiedemeier , Bruce George Rudolph , James Strom
摘要： A first oscillator signal and a second oscillator signal are transmitted to a processing unit. The first oscillator signal has a finite frequency or phase offset relative to the second oscillator signal. A first clock signal that is derived from the first oscillator signal is selected as a primary clock to clock the processing unit. A second clock signal derived from the second oscillator signal is aligned to the first clock signal. If a fault is detected on the first clock signal, the second clock signal is selected as the primary clock to clock the processing unit. Upon being selected as the primary clock, the phase of the second is stretched by one fixed phase for one clock cycle.
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公开(公告)号：US20220406769A1
公开(公告)日：2022-12-22
申请号：US17354469
申请日：2021-06-22
发明人： Dureseti Chidambarrao , Matthew Stephen Angyal , Noah Zamdmer , Varadarajan Vidya , James Strom , Grant P. Kesselring , Erik Unterborn
IPC分类号： H01L27/02
摘要： A structure is provided that includes a first active circuit in which at least one of areas surrounding the first active circuit includes an active circuit-containing region. A second active circuit is spaced apart from the first active circuit. The second active circuit includes a circuit mimic fill area present in at least one of the areas surrounding the second active circuit. The circuit mimic fill area substantially matches the active circuit-containing region that is adjacent to the first active circuit. The circuit mimic fill area is located on an equivalent side of the second active circuit as the active circuit-containing region that is present adjacent the first active circuit. The use of the circuit mimic fill mitigates the effects over medium range and beyond distances that cause device failure.
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公开(公告)号：US11527953B1
公开(公告)日：2022-12-13
申请号：US17506829
申请日：2021-10-21
摘要： A phase locked loop having a charge pump is described. The charge pump relies on close matching of FETs (Field Effect Transistor) electrical parameters to FETs in a current reference circuit. To achieve close matching of FET electrical performance, FEOL (Front End Of Line), comprising all FET shapes, of the current pump is identical in shapes and layout to the current reference circuit. BEOL (Back End Of Line) differs between the charge pump and the current reference circuit. The charge pump and the current reference circuit are arranged in a row. A shield circuit having FEOL shapes and layout identical to the current pump may be placed at each end of the row.
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公开(公告)号：US10778146B2
公开(公告)日：2020-09-15
申请号：US16011793
申请日：2018-06-19
发明人： Grant P. Kesselring , James Strom , Scott Trcka , Ann Chen Wu
摘要： A voltage-controlled oscillator (VCO) having an operating frequency dependent on a total capacitance of selectable tuning capacitors can be fabricated within an integrated circuit (IC). The VCO can include active electronic devices fabricated within a set of lower layers of the IC and selectable tuning capacitors having electrically conductive structures separated by dielectric material fabricated within a set of upper layers of the IC. The upper layers of the IC are located above the set of lower layers of the IC. The VCO can also include a set of interconnect structures configurable to select a total capacitance of the selectable tuning capacitors by electrically interconnecting the first portion of the VCO to capacitors of the at least one selectable tuning capacitor.
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公开(公告)号：US20220345085A1
公开(公告)日：2022-10-27
申请号：US17239862
申请日：2021-04-26
IPC分类号： H03B5/12
摘要： A voltage-controlled oscillator comprises a varactor. A capacitance of the first varactor is dependent upon a control voltage. The voltage-controlled also comprises an inductor. The inductor is connected to a center-tap connection. The voltage-controlled oscillator also comprises a power source. The power source is configured to provide a bias voltage to the inductor through the center-tap connection. The voltage-controlled oscillator also comprises a coupling capacitor. The coupling capacitor is located between the inductor and the varactor. The voltage-controlled oscillator also comprises a coupling resistor. The coupling resistor is located between the coupling capacitor and the center-tap connection. The center-tap connection provides the bias voltage to the coupling capacitor through the coupling resistor.
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公开(公告)号：US10897225B1
公开(公告)日：2021-01-19
申请号：US16583898
申请日：2019-09-26
摘要： A steady-state voltage on an oscillator output can be detected, independent of control signals received from other circuitry, by an oscillator failure detection circuit (OFDC) fabricated within an integrated circuit (IC). The OFDC can, in response to detecting the steady-state voltage, output an oscillator failure signal on a reference fail output. The OFDC can receive, with a first and a second buffer, an oscillator output signal from an oscillator output. Through the use of an electrically interconnected, pull-down device, pull-up network, pull-up device, pull-down network, Schmitt trigger, inverting Schmitt trigger and OR-gate, the OFDC can drive the oscillator failure signal onto an output of the OR-gate electrically connected to a reference fail output (RFO).
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