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100 条记录 (耗时 0.04 秒)

    Diffusion barrier layer formation
    1.
    发明授权
    Diffusion barrier layer formation 有权

    公开(公告)号：US10170359B2

    公开(公告)日：2019-01-01

    申请号：US15797791

    申请日：2017-10-30

    申请人： International Business Machines Corporation

    发明人： Brett H. Engel ,  Domingo A. Ferrer ,  Arun Vijayakumar ,  Keith Kwong Hon Wong

    IPC分类号： H01L21/768 ,  H01L21/285 ,  H01L23/485 ,  H01L23/532

    摘要： A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma.

    Deposition chamber cleaning method including stressed cleaning layer
    5.
    发明授权
    Deposition chamber cleaning method including stressed cleaning layer 有权
    沉积室清洗方法包括应力清洗层

    公开(公告)号：US09017487B2

    公开(公告)日：2015-04-28

    申请号：US13780449

    申请日：2013-02-28

    申请人： International Business Machines Corporation

    发明人： Tien-Jen J. Cheng ,  Zhengwen Li ,  Keith Kwong Hon Wong

    IPC分类号： B08B7/00 ,  B08B7/04 ,  C23C16/44 ,  C23C14/34

    CPC分类号： B08B7/04 ,  B08B7/0014 ,  C23C14/34 ,  C23C16/4404

    摘要： A method for cleaning a deposition chamber includes forming a deposited layer over an interior surface of the deposition chamber, wherein the deposited layer has a deposited layer stress and a deposited layer modulus; forming a cleaning layer over the deposited layer, wherein a material comprising the cleaning layer is selected such that the cleaning layer adheres to the deposited layer, and has a cleaning layer stress and a cleaning layer modulus, wherein the cleaning layer stress is higher than the deposited layer stress, and wherein the cleaning layer modulus is higher than the deposited layer modulus; and removing the deposited layer and the cleaning layer from the interior of the deposition chamber.

    摘要翻译： 清理沉积室的方法包括在沉积室的内表面上形成沉积层，其中沉积层具有沉积层应力和沉积层模量; 在所述沉积层上形成清洁层，其中选择包括所述清洁层的材料，使得所述清洁层粘附到所述沉积层，并且具有清洁层应力和清洁层模量，其中所述清洁层应力高于 沉积层应力，并且其中所述清洁层模量高于所述沉积层模量; 以及从沉积室的内部去除沉积层和清洁层。

    Scaling of metal gate with aluminum containing metal layer for threshold voltage shift
    6.
    发明授权
    Scaling of metal gate with aluminum containing metal layer for threshold voltage shift 有权
    用含金属金属层的金属栅极进行标定电压偏移

    公开(公告)号：US08901674B2

    公开(公告)日：2014-12-02

    申请号：US13775430

    申请日：2013-02-25

    申请人： International Business Machines Corporation

    发明人： Keith Kwong Hon Wong ,  Dechao Guo ,  Unoh Kwon ,  Christopher Carr Parks ,  Yun-Yu Wang

    IPC分类号： H01L21/02 ,  H01L29/02 ,  H01L21/70 ,  H01L21/8238 ,  H01L21/4763 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49 ,  H01L29/40 ,  H01L29/66

    CPC分类号： H01L29/511 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

    摘要： A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.

    摘要翻译： 提供一种形成p型半导体器件的方法，其在一个实施例中使用含铝的阈值电压移位层，以产生朝向p型半导体器件的价带的阈值电压偏移。 形成p型半导体器件的方法可以包括在衬底上形成栅极结构，其中栅极结构包括与衬底接触的栅极电介质层，存在于栅极电介质层上的含铝的阈值电压移位层， 以及与含铝的阈值电压移位层和栅极电介质层中的至少一个接触的含金属层。 P型源极和漏极区可以形成在衬底附近，栅极结构所在的衬底的相邻部分。 还提供了通过上述方法提供的p型半导体器件。

    Electrical fuses and methods of making electrical fuses
    7.
    发明授权
    Electrical fuses and methods of making electrical fuses 有权
    电气保险丝和电气保险丝的制造方法

    公开(公告)号：US08896090B2

    公开(公告)日：2014-11-25

    申请号：US13774373

    申请日：2013-02-22

    申请人： International Business Machines Corporation

    发明人： Nicholas R. Hogle ,  Baozhen Li ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

    IPC分类号： H01L29/00 ,  H01L23/525

    CPC分类号： H01L23/5256 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A fuse, a method of making the fuse and a circuit containing the fuse. The fuse includes an electrically conductive and conformal liner on sidewalls and the bottom of a trench; a copper layer on the conformal liner, a first thickness of the copper layer over the bottom of the trench in a lower portion of the trench greater than a second thickness of the copper layer over the sidewalls of the trench in an abutting upper portion of the trench; and a dielectric material on the copper layer in the trench, the dielectric material filling remaining space in the upper portion of said trench.

    摘要翻译： 保险丝，制作保险丝的方法和包含保险丝的电路。 熔丝包括在侧壁和沟槽的底部上的导电和保形衬垫; 在保形衬套上的铜层，在沟槽的下部中的沟槽的底部上的铜层的第一厚度大于第二厚度的铜层在沟槽的侧壁上的第二厚度 沟; 以及在沟槽中的铜层上的电介质材料，所述电介质材料填充所述沟槽上部的剩余空间。

    Hybrid interconnect structure for performance improvement and reliability enhancement
    8.
    发明授权
    Hybrid interconnect structure for performance improvement and reliability enhancement 有权
    混合互连结构，用于性能改进和可靠性提升

    公开(公告)号：US08796854B2

    公开(公告)日：2014-08-05

    申请号：US13838956

    申请日：2013-03-15

    申请人： International Business Machines Corporation

    发明人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keith Kwong Hon Wong ,  Haining S. Yang

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76841 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A hybrid interconnect structure (of the single or dual damascene type) is provided in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance. Moreover, the hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.

    摘要翻译： 提供了混合互连结构（单镶嵌或双镶嵌型），其中在电介质材料的侧壁上存在致密的（即非多孔的）电介质间隔物。 更具体地说，该结构包括介电材料，其具有嵌入电介质材料中至少一个开口内的导电材料，其中导电材料通过扩散阻挡层，致密电介质间隔物和任选的 气隙。 密集电介质间隔物的存在导致具有改进的可靠性和性能的混合互连结构。 此外，混合互连结构提供更好的过程控制，这导致大批量制造的潜力。

    SEMICONDUCTOR DEVICE WITH RAISED SOURCE/DRAIN AND REPLACEMENT METAL GATE
    10.
    发明申请
    SEMICONDUCTOR DEVICE WITH RAISED SOURCE/DRAIN AND REPLACEMENT METAL GATE 有权
    具有提高源/排出和更换金属栅的半导体器件

    公开(公告)号：US20140154846A1

    公开(公告)日：2014-06-05

    申请号：US13690867

    申请日：2012-11-30

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Kangguo CHENG ,  Junli Wang ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66545 ,  H01L21/28247 ,  H01L21/743 ,  H01L29/0692 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78654

    摘要： In a method of fabricating a semiconductor device, a silicon-on-insulator (SOI) substrate is provided. This SOI substrate comprises a buried oxide layer and an ETSOI layer between the buried oxide layer and a surface of the SOI substrate. A dummy gate is formed on the ETSOI. At least two raised source/drain regions are epitaxially formed adjacent to the dummy gate, and a protective cap is formed thereon. An etch process employing at least one acid is used to remove the dummy gate from the ETSOI. A gate dielectric layer is deposited on the protective cap and the ETSOI after removing the dummy gate. A replacement metal gate is then formed on the gate dielectric layer to replace the removed dummy gate, the gate dielectric layer is removed from the protective metal cap, and the protective cap is removed from the raised source/drain regions.

    摘要翻译： 在制造半导体器件的方法中，提供了绝缘体上硅（SOI）衬底。 该SOI衬底包括掩埋氧化物层和掩埋氧化物层与SOI衬底的表面之间的ETSOI层。 在ETSOI上形成一个虚拟门。 至少两个凸起的源极/漏极区域与伪栅极相邻地外延形成，并且在其上形成保护帽。 使用至少一种酸的蚀刻工艺用于从ETSOI中除去虚拟栅极。 在去除虚拟栅极之后，在保护盖和ETSOI上沉积栅极电介质层。 然后在栅极电介质层上形成置换金属栅极以取代去除的虚拟栅极，从保护金属盖上去除栅极电介质层，并且从升高的源极/漏极区域移除保护帽。