公开(公告)号：US20230275152A1

公开(公告)日：2023-08-31

申请号：US18308734

申请日：2023-04-28

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/785 ,  H01L29/41766 ,  H01L29/0847 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/1037 ,  H01L2029/7858 ,  H01L21/0262

Abstract: Embodiments of the invention are directed to a field effect transistor (FET) device including a first channel region over a first region of a substrate; a second channel region over a second region of the substrate and adjacent to the first channel region; and a bottom conductive layer over a third region of the substrate and operable to form a bottommost component of a multi-component wrap-around source or drain (S/D) contact. The first region of the substrate, the second region of the substrate, and the third region of the substrate do not overlap. The bottom conductive layer includes a non-uniform height having a first section and a second section. The first section tapers downward toward the first channel region and the second section tapers downward toward the second channel region.

公开(公告)号：US11251267B2

公开(公告)日：2022-02-15

申请号：US16684022

申请日：2019-11-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Peng Xu ,  Zheng Xu

IPC: H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/786 ,  H01L21/8238 ,  H01L27/092

Abstract: A pair of vertical fin field effect transistors (FinFETs) having different gate lengths, includes, a first bottom source/drain on a first region of a substrate, wherein the first bottom source/drain includes a first tier having a first height adjacent to a first vertical fin and a second tier having a second height greater than the first tier removed from the first vertical fin; and a second bottom source/drain on a second region of the substrate, wherein the second bottom source/drain includes a third tier having a third height adjacent to a second vertical fin and a fourth tier having a fourth height greater than the third tier removed from the second vertical fin, wherein the third height is less than the first height and the fourth height is equal to the second height.

公开(公告)号：US11101182B2

公开(公告)日：2021-08-24

申请号：US16698052

申请日：2019-11-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Choonghyun Lee ,  Juntao Li ,  Peng Xu

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/423 ,  H01L29/786 ,  H01L27/092 ,  H01L27/06 ,  H01L21/8238 ,  H01L21/822 ,  H01L21/02 ,  H01L29/06 ,  H01L29/49 ,  B82Y10/00 ,  H01L21/3065

Abstract: Integrated chips include vertically stacked channel layers, with a first stack in a first device region and a second stack in a second device region. A first dielectric layer is formed conformally on the vertically stacked channel layers in the first device region. A second dielectric layer is formed conformally on the vertically stacked channel layers in the second device region. Gate conductors are formed around the vertically stacked channel layers in both the first device region and the second device region, filling a space between surfaces of the respective first dielectric layer and second dielectric layer.

公开(公告)号：US11049940B2

公开(公告)日：2021-06-29

申请号：US16509032

申请日：2019-07-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Peng Xu ,  Kangguo Cheng ,  Juntao Li ,  Heng Wu

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/165 ,  H01L29/423 ,  H01L21/02 ,  H01L21/308 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/467

Abstract: A method of a forming a plurality of semiconductor fin structures that includes forming a sacrificial gate structure on a hardmask overlying a channel region portion of the plurality of sacrificial fins of a first semiconductor material and forming source and drain regions on opposing sides of the channel region. The sacrificial gate structure and the sacrificial fin structure are removed. A second semiconductor material is formed in an opening provided by removing the sacrificial gate structure and the sacrificial fin structure. The second semiconductor material is etched selective to the hardmask to provide a plurality of second semiconductor material fin structures. A function gate structure is formed on the channel region.

公开(公告)号：US10957599B2

公开(公告)日：2021-03-23

申请号：US16182848

申请日：2018-11-07

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Junli Wang ,  Peng Xu

IPC: H01L29/76 ,  H01L21/8234 ,  H01L27/088

Abstract: Embodiments of the present invention are directed to techniques for integrating an extra gate (EG) vertical field effect transistor (VFET) with a single gate (SG) VFET. In a non-limiting embodiment of the invention, a bottom source or drain (S/D) layer is formed over a substrate. A first semiconductor fin is formed over the bottom S/D layer in a first region of the substrate and a second semiconductor fin is formed over the bottom S/D layer in a second region of the substrate. A block mask is formed over the first semiconductor fin and the second semiconductor fin is recessed. The second semiconductor fin is exposed to an isotropic or anisotropic fin trim.

公开(公告)号：US10937866B2

公开(公告)日：2021-03-02

申请号：US16509061

申请日：2019-07-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Peng Xu ,  Kangguo Cheng ,  Juntao Li ,  Heng Wu

IPC: H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L21/308 ,  H01L21/762 ,  H01L21/3065 ,  H01L29/40 ,  H01L29/78 ,  H01L29/165 ,  H01L21/467

Abstract: A method of a forming a plurality of semiconductor fin structures that includes forming a sacrificial gate structure on a hardmask overlying a channel region portion of the plurality of sacrificial fins of a first semiconductor material and forming source and drain regions on opposing sides of the channel region. The sacrificial gate structure and the sacrificial fin structure are removed. A second semiconductor material is formed in an opening provided by removing the sacrificial gate structure and the sacrificial fin structure. The second semiconductor material is etched selective to the hardmask to provide a plurality of second semiconductor material fin structures. A function gate structure is formed on the channel region.

公开(公告)号：US10892325B2

公开(公告)日：2021-01-12

申请号：US16455096

申请日：2019-06-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Juntao Li ,  Kangguo Cheng ,  Choonghyun Lee ,  Peng Xu

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: A method of forming a fin field effect transistor device is provided. The method includes forming a vertical fin layer on a bottom source/drain layer, and forming one or more fin templates on the vertical fin layer. The method further includes forming a vertical fin below each of the one or more fin templates. The method further includes reducing the width of each of the vertical fins to form one or more thinned vertical fins, wherein at least a portion of the fin template overhangs the sides of the underlying thinned vertical fin. The method further includes depositing a bottom spacer layer on the bottom source/drain layer, wherein the bottom spacer layer has a non-uniform thickness that tapers in a direction towards the thinned vertical fins.

公开(公告)号：US10886169B2

公开(公告)日：2021-01-05

申请号：US16598458

申请日：2019-10-10

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ekmini A. De Silva ,  Juntao Li ,  Yi Song ,  Peng Xu

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/762 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/027

Abstract: A method and structure of forming air gaps with a sidewall image transfer process such as self-aligned double patterning to reduce capacitances. Different materials can be provided in the mandrel and non-mandrel regions to enlarge a process window for metal line end formation.

公开(公告)号：US10784333B2

公开(公告)日：2020-09-22

申请号：US16456610

申请日：2019-06-28

Applicant: International Business Machines Corporation

Inventor： Peng Xu ,  Kangguo Cheng ,  Xuefeng Liu ,  Chi-Chun Liu ,  Yongan Xu

IPC: H01L49/02 ,  H01L21/3105 ,  H01L23/522

Abstract: Techniques for generating enhanced inductors and other electronic devices are presented. A device generator component (DGC) performs directed-self assembly (DSA) co-polymer deposition on a circular guide pattern formed in low-k dielectric film, and DSA annealing to form two polymers in the form of alternating concentric rings; performs a loop cut in the concentric rings to form concentric segments; fills the cut portion with insulator material; selectively removes first polymer, fills the space with low-k dielectric, and planarizes the surface; selectively removes the second polymer, fills the space with conductive material, and planarizes the surface; deposits low-k film on top of the concentric segments and insulator material that filled the loop cut portion; forms vias in the low-k film, wherein each via spans from an end of one segment to an end of another segment; and fills vias with conductive material to form conductive connectors to form substantially spiral conductive structure.

公开(公告)号：US20200266195A1

公开(公告)日：2020-08-20

申请号：US16866150

申请日：2020-05-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A method of forming vertical fins on a substrate at the same time, the method including, forming a mask segment on a first region of the substrate while exposing the surface of a second region of the substrate, removing a portion of the substrate in the second region to form a recess, forming a fin layer in the recess, where the fin layer has a different material composition than the substrate, and forming at least one vertical fin on the first region of the substrate and at least one vertical fin on the second region of the substrate, where the vertical fin on the second region of the substrate includes a fin layer pillar formed from the fin layer and a substrate pillar.