-
公开(公告)号：US20210035813A1
公开(公告)日：2021-02-04
申请号：US16530165
申请日：2019-08-02
发明人： Hari Prasad Amanapu , Comelius Brown Peethala , Iqbal Rashid Saraf , Raghuveer Reddy Patlolla , Chih-Chao Yang
IPC分类号： H01L21/3105 , H01L21/02 , H01L21/311
摘要： Techniques for planarization of dielectric topography that stop in dielectric are provided. In one aspect, a method for planarization includes: depositing a first dielectric onto a wafer having a surface topography with peaks and valleys; depositing a second, different dielectric onto the first dielectric; and polishing the second dielectric down to the first dielectric to form a planar surface at an interface between the first dielectric and the second dielectric. Optionally, a follow-up CMP or etch can be performed using a ˜1:1 selective polish or etch to completely remove the second dielectric and an equivalent amount of the first dielectric to form a planar surface devoid of the peaks and valleys in the first dielectric. A device structure formed by the present techniques is also provided.
-
2.发明授权公开(公告)号：US11164878B2
公开(公告)日：2021-11-02
申请号：US16777540
申请日：2020-01-30
IPC分类号： H01L27/088 , H01L27/24 , H01L27/22 , H01L27/108
摘要： Interconnect structures or memory structures are provided in the BEOL in which topography variation is reduced. Reduced topography variation is achieved by providing a structure that includes a first dielectric capping layer that has a planar topmost surface and/or a second dielectric capping layer that has a planar topmost surface. The first dielectric capping layer has a non-planar bottom surface that contacts both a recessed surface of an interconnect dielectric material layer and a planar topmost surface of at least one electrically conductive structure that is embedded in the interconnect dielectric material layer.
-
公开(公告)号：US20210242077A1
公开(公告)日：2021-08-05
申请号：US16776982
申请日：2020-01-30
发明人： Cornelius Brown Peethala , Hari Prasad Amanapu , Raghuveer Reddy Patlolla , Koichi Motoyama , Chih-Chao Yang
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
摘要： Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first dielectric layer from a first dielectric material. A first conductive interconnect is formed having a first conductive interconnect surface. The first conductive interconnect is positioned in a first portion of the first dielectric layer, and the first conductive interconnect surface has a first conductive interconnect surface area. A second conductive interconnect is formed having a second conductive interconnect surface. The second conductive interconnect is above the first conductive interconnect and positioned in a second portion of the first dielectric layer. The second conductive interconnect surface has a second conductive interconnect surface area that is less than a first conductive interconnect surface area of the first conductive interconnect. A planarization stop region is formed above the second conductive interconnect and in a third portion of the first dielectric layer.
-
公开(公告)号：US10916431B2
公开(公告)日：2021-02-09
申请号：US16385668
申请日：2019-04-16
发明人： Raghuveer Reddy Patlolla , Hari Prasad Amanapu , Vimal Kamineni , Sugirtha Krishnamurthy , Viraj Yashawant Sardesai , Cornelius Brown Peethala
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L21/28 , H01L21/768 , H01L29/49
摘要： Embodiments of the invention describe a method of forming an integrated circuit. The method includes forming an active semiconductor device region over a substrate. A first contact structure is formed over the active semiconductor device region, wherein the first contact structure includes a first contact liner material and a first contact body material. A conductive gate structure is formed over the active semiconductor device region, and a first gate cap material is formed on the conductive gate structure. The first contact liner material includes a first etch selectivity responsive to a first etch composition, the first contact body material includes a second etch selectivity responsive to the first etch composition, and the first gate cap material includes a third etch selectivity responsive to the first etch composition. The first etch selectivity is greater than each of the second and third etch selectivies.
-
公开(公告)号：US20200350201A1
公开(公告)日：2020-11-05
申请号：US16401180
申请日：2019-05-02
发明人： Koichi Motoyama , Oscar van der Straten , Joseph F. Maniscalco , Alexander Reznicek , Raghuveer Reddy Patlolla , Theodorus E. Standaert
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
摘要： A method including forming a dual damascene interconnect structure comprising a metal wire above a via, recessing the metal wire to form a trench, depositing a liner along a bottom and a sidewall of the trench, and forming a new metal wire in the trench. The method may also include forming a dual damascene interconnect structure comprising a metal wire above a via, recessing the metal wire to form a trench, depositing a liner along a bottom and a sidewall of the trench, removing the liner along the bottom of the trench, and forming a new metal wire in the trench.
-
公开(公告)号：US11637036B2
公开(公告)日：2023-04-25
申请号：US16776982
申请日：2020-01-30
发明人： Cornelius Brown Peethala , Hari Prasad Amanapu , Raghuveer Reddy Patlolla , Koichi Motoyama , Chih-Chao Yang
IPC分类号： H01L21/768 , H01L23/532 , H01L23/522 , H01L21/762 , H01L43/08 , H01L43/12
摘要： Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first dielectric layer from a first dielectric material. A first conductive interconnect is formed having a first conductive interconnect surface. The first conductive interconnect is positioned in a first portion of the first dielectric layer, and the first conductive interconnect surface has a first conductive interconnect surface area. A second conductive interconnect is formed having a second conductive interconnect surface. The second conductive interconnect is above the first conductive interconnect and positioned in a second portion of the first dielectric layer. The second conductive interconnect surface has a second conductive interconnect surface area that is less than a first conductive interconnect surface area of the first conductive interconnect. A planarization stop region is formed above the second conductive interconnect and in a third portion of the first dielectric layer.
-
7.发明申请公开(公告)号：US20210242216A1
公开(公告)日：2021-08-05
申请号：US16777540
申请日：2020-01-30
IPC分类号： H01L27/108 , H01L27/22 , H01L27/24 , H01L27/088
摘要： Interconnect structures or memory structures are provided in the BEOL in which topography variation is reduced. Reduced topography variation is achieved by providing a structure that includes a first dielectric capping layer that has a planar topmost surface and/or a second dielectric capping layer that has a planar topmost surface. The first dielectric capping layer has a non-planar bottom surface that contacts both a recessed surface of an interconnect dielectric material layer and a planar topmost surface of at least one electrically conductive structure that is embedded in the interconnect dielectric material layer.
-
公开(公告)号：US11037795B2
公开(公告)日：2021-06-15
申请号：US16530165
申请日：2019-08-02
发明人： Hari Prasad Amanapu , Cornelius Brown Peethala , Iqbal Rashid Saraf , Raghuveer Reddy Patlolla , Chih-Chao Yang
IPC分类号： H01L21/3105 , H01L21/02 , H01L21/311
摘要： Techniques for planarization of dielectric topography that stop in dielectric are provided. In one aspect, a method for planarization includes: depositing a first dielectric onto a wafer having a surface topography with peaks and valleys; depositing a second, different dielectric onto the first dielectric; and polishing the second dielectric down to the first dielectric to form a planar surface at an interface between the first dielectric and the second dielectric. Optionally, a follow-up CMP or etch can be performed using a ˜1:1 selective polish or etch to completely remove the second dielectric and an equivalent amount of the first dielectric to form a planar surface devoid of the peaks and valleys in the first dielectric. A device structure formed by the present techniques is also provided.
-
公开(公告)号：US20200335345A1
公开(公告)日：2020-10-22
申请号：US16385668
申请日：2019-04-16
发明人： Raghuveer Reddy Patlolla , Hari Prasad Amanapu , Vimal Kamineni , Sugirtha Krishnamurthy , Viraj Yashawant Sardesai , Cornelius Brown Peethala
IPC分类号： H01L21/28 , H01L29/49 , H01L21/768
摘要： Embodiments of the invention describe a method of forming an integrated circuit. The method includes forming an active semiconductor device region over a substrate. A first contact structure is formed over the active semiconductor device region, wherein the first contact structure includes a first contact liner material and a first contact body material. A conductive gate structure is formed over the active semiconductor device region, and a first gate cap material is formed on the conductive gate structure. The first contact liner material includes a first etch selectivity responsive to a first etch composition, the first contact body material includes a second etch selectivity responsive to the first etch composition, and the first gate cap material includes a third etch selectivity responsive to the first etch composition. The first etch selectivity is greater than each of the second and third etch selectivies.
-
-
-
-
-
-
-
-
搜索结果
9 条记录 (耗时 0.011 秒)