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公开(公告)号：US20230110073A1
公开(公告)日：2023-04-13
申请号：US17485580
申请日：2021-09-27
发明人： Ruilong Xie , Julien Frougier , Kangguo Cheng , Chanro Park
IPC分类号： H01L29/78 , H01L27/088 , H01L29/06 , H01L23/522 , H01L23/528 , H01L29/66 , H01L21/8234
摘要： A semiconductor structure includes a substrate and a field effect transistor disposed on the substrate. The field effect transistor includes a vertical fin, source and drain regions separated by a gate region, a gate structure disposed over the gate region and a gate airgap spacer at least partially disposed about the gate structure.
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公开(公告)号：US20230100113A1
公开(公告)日：2023-03-30
申请号：US17488389
申请日：2021-09-29
发明人： Ruilong Xie , Stuart Sieg , Somnath Ghosh , Kisik Choi , Rishikesh Krishnan , Alexander Reznicek
IPC分类号： H01L23/528 , H01L23/522 , H01L21/768 , H01L21/311
摘要： Integrated chips and methods of forming the same include forming a stack of layers, including a device stack above a first sacrificial layer, above a substrate. The first sacrificial layer is replaced with a first etch stop layer. The substrate is removed, exposing a substrate-side of the stack of layers. The substrate-side of the stack of layers is etched to form a trench, stopping on the first etch stop layer. A conductive line is formed in the trench.
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公开(公告)号：US20230098033A1
公开(公告)日：2023-03-30
申请号：US17485768
申请日：2021-09-27
摘要： A device includes a plurality of magnetic random-access memory (MRAM) cells in a first region of the device; and a dummy MRAM pillar disposed in a second region of the device, wherein the dummy MRAM pillar is not connected to an active metal feature.
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4.发明授权公开(公告)号：US11615990B2
公开(公告)日：2023-03-28
申请号：US16828619
申请日：2020-03-24
发明人： Heng Wu , Ruilong Xie , Su Chen Fan , Jay William Strane , Hemanth Jagannathan
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/78 , H01L29/06 , H01L21/265 , H01L29/66
摘要： A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling.
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公开(公告)号：US11605717B2
公开(公告)日：2023-03-14
申请号：US17125775
申请日：2020-12-17
发明人： Ruilong Xie , Eric Miller , Jeffrey C. Shearer , Su Chen Fan , Heng Wu
IPC分类号： H01L29/40 , H01L29/08 , H01L29/417 , H01L29/66 , H01L29/78
摘要： A semiconductor structure and a method of making the same includes a first recessed region in a semiconductor structure, the first recessed region defining a first opening with a first positive tapering profile, as at least part of the first positive tapering profile, widening the first opening in a direction towards a top source/drain region of the semiconductor structure at a first tapering angle, and a top source/drain contact within the first opening, the top source/drain contact surrounding a surface of the top source/drain region. The semiconductor structure further includes a protective liner located at an interface between a bottom portion of the top source/drain region, a top spacer adjacent to the top source/drain region and a dielectric material between two consecutive top source/drain regions, the protective liner protects the top source/drain regions during contact patterning.
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公开(公告)号：US20230074676A1
公开(公告)日：2023-03-09
申请号：US17469350
申请日：2021-09-08
摘要： An approach for minimizing stack height and reducing resistance of an MRAM (Magnetoresistive random-access memory) is disclosed. The approach leverages an MRAM device with a T shape magnetic bottom electrode. The T shape magnetic bottom electrode u can be made a lower resistance metal such as cobalt. Furthermore, the method of creating the MRAM can include, depositing a low-k dielectric layer, forming bottom electrode via within the low-k dielectric layer, depositing bottom electrode metal liner on the bottom electrode via, depositing bottom electrode magnetic metal on the bottom electrode metal liner, planarizing the bottom electrode magnetic metal, depositing coupling layer and an MRAM stack on the bottom electrode magnetic metal, patterning and etching anisotropically the MRAM stack and depositing in-situ conformal dielectric layer and forming a top contact via on the MRAM stack.
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公开(公告)号：US20230066107A1
公开(公告)日：2023-03-02
申请号：US17412776
申请日：2021-08-26
发明人： Ruilong Xie , Alexander Reznicek , Wei Wang , Tao Li , Tsung-Sheng Kang
摘要： An integrated circuit, a system, and a method to integrate phase change memory and magnetoresistive random access memory within a same integrated circuit in a system. The integrated circuit may include an MRAM and a PCM. The MRAM may include an MRAM bottom electrode, an MRAM stack, and an MRAM top electrode. The PCM may include a PCM bottom electrode, where the PCM bottom electrode has a lower height than the MRAM bottom electrode, a phase change material, and a PCM top electrode.
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公开(公告)号：US20230063973A1
公开(公告)日：2023-03-02
申请号：US17446626
申请日：2021-09-01
发明人： Ruilong Xie , Chen Zhang , Brent Anderson , Robert Robison , Ardasheir Rahman , Hemanth Jagannathan
IPC分类号： H01L27/06 , H01L29/78 , H01L21/8234
摘要： An apparatus comprising a plurality of FET columns located on a substrate. A source/drain layer located around the base of the plurality of FET columns. A dielectric layer located around the source/drain layer, wherein a portion of the dielectric layer that is sandwiched between a first portion of the source/drain layer and a second portion of the source/drain layer. A gate layer, wherein the gate layer has a first portion located on top of the source/drain layer, and wherein the gate layer has a second portion located on top of the portion of the dielectric layer that is sandwiched between a first portion of the source/drain layer and a second portion of the source/drain layer.
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公开(公告)号：US20230054701A1
公开(公告)日：2023-02-23
申请号：US17406351
申请日：2021-08-19
发明人： Ruilong Xie , Kangguo Cheng , JUNTAO LI , Carl Radens
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12
摘要： An approach for a nanosheet device with a single diffusion break is disclosed. The device comprises of active gate is formed above the BDI. At least the SDB is also formed over BDI with dielectric filled gate. The dielectric fill forms an indentation into the remaining nanosheets, under the spacer region, or between the inner spacers, in the SDB region. The method of creating the device comprises of, forming a gate cut opening between two ends of a dummy gate of one or more gates; forming a first sacrificial material on the gate cut opening; creating a single diffusion break; removing the dummy gate and oxide layer; removing, selectively a second sacrificial material; trimming, selectively stack of nanosheets; and forming dielectric in the gate cut opening and the single diffusion break.
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公开(公告)号：US20230038116A1
公开(公告)日：2023-02-09
申请号：US17397242
申请日：2021-08-09
IPC分类号： H01L27/092 , H01L29/06 , H01L29/423 , H01L29/786 , H01L21/02 , H01L21/8238 , H01L29/66
摘要： A forksheet transistor device includes a dual dielectric pillar that includes a first dielectric and a second dielectric that is different from the first dielectric. The dual dielectric pillar physically separates pFET elements from nFET elements. For example, the first dielectric physically separates a pFET gate from a nFET gate while the second dielectric physically separates a pFET source/drain region from a nFET source drain region. When it is advantageous to electrically connect the pFET gate and the nFET gate, the first dielectric may be etched selective to the second dielectric to form a gate connector trench within the dual dielectric pillar. Subsequently, an electrically conductive gate connector strap may be formed within the gate connector trench to electrically connect the pFET gate and the nFET gate.
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