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公开(公告)号：US11112854B2
公开(公告)日：2021-09-07
申请号：US16432524
申请日：2019-06-05
发明人： Steven M. Douskey , Raghu G. Gopalakrishnasetty , Mary P. Kusko , Hari Krishnan Rajeev , James D. Warnock
IPC分类号： G06F1/32 , G06F1/26 , G06F1/3287 , G06F1/3296
摘要： Operating pulsed latches on a variable power supply including turning on a first power rail powering a first latch of an integrated circuit, wherein the first latch is a pulsed latch; turning on a second power rail powering a second latch of the integrated circuit, wherein the second latch is operatively coupled to the first latch; performing a scan operation using the first latch and the second latch; turning off the first power rail powering the first latch; and performing a functional operation using the second latch, wherein the first power rail powering the first latch is off during the functional operation.
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公开(公告)号：US10816599B2
公开(公告)日：2020-10-27
申请号：US16249074
申请日：2019-01-16
IPC分类号： G01R31/3177 , G01R31/317 , G01R31/3183 , G01R31/3181 , G01R31/3185
摘要： Method and apparatus to test an integrated circuit includes retrieving power distribution data relating to an integrated circuit and designating a segment that includes at least one component of the integrated circuit. A switching limit associated with the segment may be set based on the power distribution data. Processes further generate a testing pattern that includes the determined switching limit associated with the segment.
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公开(公告)号：US10359471B2
公开(公告)日：2019-07-23
申请号：US15178240
申请日：2016-06-09
IPC分类号： G01R31/3177 , G01R31/317 , G01R31/327
摘要： A method and circuit for implementing enhanced scan data testing with decreased scan data interdependence for compressed patterns in on product multiple input signature register (OPMISR) testing through scan skewing, and a design structure on which the subject circuit resides are provided. The circuit is divided into multiple chiplets. Each chiplet includes a stump mux structure including multiple stump muxes connected in series, and a respective chiplet select is provided on shared scan inputs to respective chiplets. The chiplet select gates scan clocks, and when a chiplet is not selected the chiplet retains its data. The chiplet select enables test data to be skewed as scan data enters each chiplet.
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4.发明授权Inserting bypass structures at tap points to reduce latch dependency during scan testing 有权在分接点插入旁路结构，以减少扫描测试期间的锁存依存性公开(公告)号：US09547039B2
公开(公告)日：2017-01-17
申请号：US14574613
申请日：2014-12-18
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185
CPC分类号： G01R31/3172 , G01R31/318541 , G01R31/318544 , G01R31/318594
摘要： A method and apparatus are provided to test an integrated circuit by identifying first and second components of an integrated circuit. The first and second components may share a relationship that causes the first and second components to generate a matching binary output in response to an input to the integrated circuit. A tap point may be selected within the integrated circuit. The tap point may be located at a point in the integrated circuit where an insertion of a bypass structure would affect the relationship. The bypass structure may be inserted at the tap point, and the bypass structure may be used to conduct a test of the integrated circuit.
摘要翻译： 提供了一种通过识别集成电路的第一和第二组件来测试集成电路的方法和装置。 第一和第二组件可以共享使得第一和第二组件响应于集成电路的输入而产生匹配的二进制输出的关系。 可以在集成电路内选择分接点。 分接点可以位于集成电路中的旁路结构的插入将影响关系的点处。 旁路结构可以插入到抽头点处，并且旁路结构可以用于进行集成电路的测试。
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5.发明授权Partitioned scan chain diagnostics using multiple bypass structures and injection points 有权使用多个旁路结构和注入点进行分区扫描链诊断公开(公告)号：US09529046B2
公开(公告)日：2016-12-27
申请号：US14573975
申请日：2014-12-17
IPC分类号： G01R31/3177 , G06F11/00 , G06F11/25 , G06F7/02 , G01R31/3185
CPC分类号： G01R31/318583 , G01R31/318563
摘要： A method and apparatus are provided for isolating a defect in a scan chain comprising a plurality of components of an integrated circuit. A plurality of injection points may be positioned along the scan chain. Each injection point may be configured to introduce binary test data. A plurality of bypass structures may each be configured to selectively direct a flow of the binary test data to generate a plurality of partitioned scan paths. Test logic may be configured to execute a plurality of tests using the plurality of partitioned scan paths and to combine results of the plurality of tests to isolate a faulty component of the plurality of components.
摘要翻译： 提供了一种用于隔离包括集成电路的多个部件的扫描链中的缺陷的方法和装置。 多个注入点可以沿扫描链定位。 每个注入点可以被配置为引入二进制测试数据。 多个旁路结构可以各自被配置为选择性地引导二进制测试数据的流以生成多个分割的扫描路径。 测试逻辑可以被配置为使用多个分割的扫描路径执行多个测试，并且组合多个测试的结果来隔离多个分量的故障分量。
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公开(公告)号：US09429621B2
公开(公告)日：2016-08-30
申请号：US14606145
申请日：2015-01-27
IPC分类号： G01R31/28 , G01R31/3177
CPC分类号： G01R31/318563 , G01R31/318558
摘要： A method and system for implementing enhanced scan chain diagnostics via a bypass multiplexing structure. A full scan chain structure is partitioned into a plurality of separate chains, such as three separate partitioned chains, with bypass multiplexers for implementing enhanced scan chain diagnostics. Each of the separate partitioned chains includes bypass multiplexers with independent controls enabling scan data being routed through multiple different independent scan paths, potentially bypassing failing latches. The information acquired from a combination of full scans and partitioned scans is used for scan failure isolation to enable pinpoint identification of stuck-at-zero (SA0) and stuck-at-one (SA1) faults in the scan chain.
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公开(公告)号：US20160169969A1
公开(公告)日：2016-06-16
申请号：US14573975
申请日：2014-12-17
IPC分类号： G01R31/3177
CPC分类号： G01R31/318583 , G01R31/318563
摘要： A method and apparatus are provided for isolating a defect in a scan chain comprising a plurality of components of an integrated circuit. A plurality of injection points may be positioned along the scan chain. Each injection point may be configured to introduce binary test data. A plurality of bypass structures may each be configured to selectively direct a flow of the binary test data to generate a plurality of partitioned scan paths. Test logic may be configured to execute a plurality of tests using the plurality of partitioned scan paths and to combine results of the plurality of tests to isolate a faulty component of the plurality of components.
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公开(公告)号：US20160169967A1
公开(公告)日：2016-06-16
申请号：US14568312
申请日：2014-12-12
IPC分类号： G01R31/3177 , G01R31/317
CPC分类号： G01R31/3172 , G01R31/318541 , G01R31/318544 , G01R31/318594
摘要： A method and apparatus are provided to test an integrated circuit by identifying first and second components of an integrated circuit. The first and second components may share a relationship that causes the first and second components to generate a matching binary output in response to an input to the integrated circuit. A tap point may be selected within the integrated circuit. The tap point may be located at a point in the integrated circuit where an insertion of a bypass structure would affect the relationship. The bypass structure may be inserted at the tap point, and the bypass structure may be used to conduct a test of the integrated circuit.
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公开(公告)号：US09116205B2
公开(公告)日：2015-08-25
申请号：US13628231
申请日：2012-09-27
IPC分类号： G01R31/3177 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/318544 , G01R31/318563
摘要： An apparatus and method is provided for switching input pins to scan channels to increase test coverage. In one embodiment, a scan system connects a small number of input pins to several scan channels so that the input pins may be selectively switched. The input pins may transmit independent test vectors to test a large number of test areas on a semiconductor chip. The scan system may include a switching device such as a multiplexer (MUX).
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公开(公告)号：US09069041B2
公开(公告)日：2015-06-30
申请号：US13705353
申请日：2012-12-05
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3177
CPC分类号： G01R31/31703 , G01R31/31718 , G01R31/3177
摘要： A method and structure tests a system on a chip (SoC) or other integrated circuit having multiple cores for chip characterization to produce a partial good status. A Self Evaluation Engine (SEE) on each core creates a quality metric or partial good value for the core. The SEE executes one or more tests to create a characterization signature for the core. The SEE then compares the characterization signature of a core with a characterization signature of neighboring cores to determine the partial good value for the core. The SEE may output a result to create a full characterization map for detailed diagnostics or a partial good map with values for all cores to produce a partial good status for the entire SoC.
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