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    CMOS-MEMS integration by sequential bonding method
    3.
    发明授权
    CMOS-MEMS integration by sequential bonding method 有权

    公开(公告)号：US09761557B2

    公开(公告)日：2017-09-12

    申请号：US14696994

    申请日：2015-04-27

    申请人： InvenSense, Inc.

    发明人： Jong Il Shin ,  Peter Smeys ,  Jongwoo Shin

    IPC分类号： H01L23/00 ,  B81C1/00

    CPC分类号： H01L24/83 ,  B81B2207/012 ,  B81C1/00238 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/0792 ,  H01L2224/83065 ,  H01L2224/83805 ,  H01L2224/83951

    摘要： Methods for bonding two wafers are disclosed. In one aspect, a first wafer includes an integrated circuit and the second wafer including a MEMS device. The method comprises depositing a bond pad on a metal on the first wafer and sequentially bonding the first wafer to the second wafer utilizing first and second temperatures. The second wafer is bonded to the bond pad at the first temperature and the bond pad and the metal are bonded at the second temperature. In another aspect, a first wafer including an integrated circuit, the second wafer includes a MEMS device. The method comprises depositing a bond pad on a metal on one of the first wafer and the second wafer and bonding the first wafer to the second wafer at a first temperature via a direct bond interface. The method includes bonding the bond pad to the metal at a second temperature.

    MEMS-CMOS device that minimizes outgassing and methods of manufacture
    4.
    发明授权
    MEMS-CMOS device that minimizes outgassing and methods of manufacture 有权
    最小化除气的MEMS-CMOS器件和制造方法

    公开(公告)号：US09540228B2

    公开(公告)日：2017-01-10

    申请号：US14748012

    申请日：2015-06-23

    申请人： InvenSense, Inc.

    发明人： Peter Smeys ,  Jong Il Shin ,  Jongwoo Shin

    IPC分类号： B81B7/00 ,  B81C1/00

    CPC分类号： B81B7/0041 ,  B81B2207/012 ,  B81B2207/094 ,  B81C1/00293 ,  B81C2201/013 ,  B81C2201/0133 ,  B81C2201/016 ,  B81C2203/035 ,  B81C2203/0792

    摘要： A MEMS device is disclosed. The MEMS device includes a first substrate. At least one structure is formed within the first substrate. The first substrate includes at least one first conductive pad thereon. The MEMS device also includes a second substrate. The second substrate includes a passivation layer. The passivation layer includes a plurality of layers. A top layer of the plurality of layers comprises an outgassing barrier layer. At least one second conductive pad and at least one electrode are coupled to the top layer. At least one first conductive pad is coupled to the at least one second conductive pad.

    摘要翻译： 公开了MEMS器件。 MEMS器件包括第一衬底。 在第一基板内形成至少一个结构。 第一衬底包括至少一个第一导电焊盘。 MEMS器件还包括第二衬底。 第二基板包括钝化层。 钝化层包括多个层。 多个层的顶层包括除气阻挡层。 至少一个第二导电焊盘和至少一个电极耦合到顶层。 至少一个第一导电焊盘耦合到所述至少一个第二导电焊盘。

    CMOS-MEMS integrated device including multiple cavities at different controlled pressures and methods of manufacture
    5.
    发明授权
    CMOS-MEMS integrated device including multiple cavities at different controlled pressures and methods of manufacture 有权

    公开(公告)号：US10221065B2

    公开(公告)日：2019-03-05

    申请号：US15461270

    申请日：2017-03-16

    申请人： INVENSENSE, INC.

    发明人： Daesung Lee ,  Jongwoo Shin ,  Jong Il Shin ,  Peter Smeys ,  Martin Lim

    IPC分类号： H01L23/02 ,  B81C1/00 ,  B81B7/00 ,  B81B7/02

    摘要： An integrated MEMS device comprises two substrates where the first and second substrates are coupled together and have two enclosures there between. One of the first and second substrates includes an outgassing source layer and an outgassing barrier layer to adjust pressure within the two enclosures. The method includes depositing and patterning an outgassing source layer and a first outgassing barrier layer on the substrate, resulting in two cross-sections. In one of the two cross-sections a top surface of the outgassing source layer is not covered by the outgassing barrier layer and in the other of the two cross-sections the outgassing source layer is encapsulated in the outgassing barrier layer. The method also includes depositing conformally a second outgassing barrier layer and etching the second outgassing barrier layer such that a spacer of the second outgassing barrier layer is left on sidewalls of the outgassing source layer.

    FILM INDUCED INTERFACE ROUGHENING AND METHOD OF PRODUCING THE SAME
    9.
    发明申请
    FILM INDUCED INTERFACE ROUGHENING AND METHOD OF PRODUCING THE SAME 有权
    电影诱导界面粗化及其生产方法

    公开(公告)号：US20160115016A1

    公开(公告)日：2016-04-28

    申请号：US14667169

    申请日：2015-03-24

    申请人： INVENSENSE, INC.

    发明人： Fang Liu ,  Martin Lim ,  Jong Il Shin ,  Jongwoo Shin

    IPC分类号： B81C1/00

    CPC分类号： B81B3/001 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C2201/115 ,  B81C2203/0792

    摘要： Various embodiments provide for a method for roughening a surface of a MEMs device or the surface of a CMOS surface. A first material can be deposited in a thin layer over a surface made of a second material. After heating, the first and second materials, they can partially melt and interdiffuse, forming an alloy. The first material can then be removed and the alloy is removed at the same time. The surface of the second material that is left behind has then been roughened due to the interdiffusion of the first and second materials.

    摘要翻译： 各种实施例提供了用于使MEM器件的表面或CMOS表面的表面粗糙化的方法。 第一材料可以沉积在由第二材料制成的表面上的薄层中。 加热后，第一和第二种材料，它们可以部分熔化和相互扩散，形成合金。 然后可以除去第一种材料并同时去除合金。 然后由于第一和第二材料的相互扩散，留下的第二材料的表面被粗糙化。

    MEMS gap control structures
    10.
    发明授权
    MEMS gap control structures 有权

    公开(公告)号：US10829367B2

    公开(公告)日：2020-11-10

    申请号：US16389472

    申请日：2019-04-19

    申请人： InvenSense, Inc.

    发明人： Jong Il Shin ,  Peter Smeys ,  Bongsang Kim

    IPC分类号： B81B3/00 ,  B81B7/00 ,  B81C1/00 ,  H01L23/02 ,  H01L29/84 ,  B81B7/02

    摘要： Provided herein is an apparatus including a cavity in a first side of a first silicon wafer, and an oxide layer on the first side and in the cavity. A first side of a second silicon wafer is bonded to the first side of the first silicon wafer. A gap control structure is on a second side of the second silicon wafer, and a MEMS structure in the second silicon wafer. A eutectic bond is bonding the second side of the second silicon wafer to a third silicon wafer. A lower cavity is between the second side of the silicon wafer and the third silicon wafer, wherein the gap control structure is outside of the lower cavity and the eutectic bond.