Image sensor device
    1.
    发明授权

    公开(公告)号:US11069734B2

    公开(公告)日:2021-07-20

    申请号:US16513489

    申请日:2019-07-16

    发明人: Rajesh Katkar

    摘要: Methods of forming a back side image sensor device, as well as back side image sensor devices formed, are disclosed. In one such a method, an image sensor wafer having a first dielectric layer with a first surface is obtained. A reconstituted wafer having a processor die and a second dielectric layer with a second surface is obtained. The reconstituted wafer and the image sensor wafer are bonded to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer. In another method, such formation is for a processor die bonded to an image sensor wafer. In yet another method, such formation is for a processor die bonded to an image sensor die.

    Remote optical engine for virtual reality or augmented reality headsets

    公开(公告)号:US10802285B2

    公开(公告)日:2020-10-13

    申请号:US16292705

    申请日:2019-03-05

    IPC分类号: G09G5/00 G02B27/01

    摘要: A virtual reality/augmented reality (VR/AR) headset system (including the capability for one or both of virtual reality and augmented reality) includes a remote optical engine. The remote disposition of the optical engine removes many or all of the components of the VR/AR headset system that add weight, heat, and other characteristics that can add to user discomfort in using the system from the headset. An electronic image is received and/or generated remotely at the optical engine, and is transmitted optically from the remote location to the headset to be viewed by the user. One or more optical waveguides may be used to transmit the electronic image to one or more passive displays of the headset, from the remote optical engine.

    Fan-out wafer level package with resist vias

    公开(公告)号:US10593563B2

    公开(公告)日:2020-03-17

    申请号:US15873218

    申请日:2018-01-17

    摘要: Fan-out wafer level packages with resist vias are provided. In an implementation, an example wafer level process or panel fabrication process includes adhering a die to a carrier, applying a temporary resist layer over the die and the carrier, developing the resist layer to form channels or spaces, filling the channels or the spaces with a molding material, removing the remaining resist to create vias in the molding material, and metalizing the vias in the molding material to provide conductive vias for the microelectronics package. The methods automatically create good via and pad alignment. In another implementation, an example process includes adhering a die to a carrier, applying a permanent resist layer over the die and the carrier, developing the resist layer to form vias in the resist layer, and metalizing the vias in the remaining resist of the permanent resist layer to provide conductive vias for the microelectronics package. Assemblies may be constructed with the semiconductor dies face-up or face-down. One or more redistribution layers (RDLs) may be built on one or both sides of an assembly with resist vias.

    Multi-surface edge pads for vertical mount packages and methods of making package stacks

    公开(公告)号:US10354945B2

    公开(公告)日:2019-07-16

    申请号:US15660718

    申请日:2017-07-26

    摘要: Multi-surface edge pads for vertical mount packages and methods of making package stacks are provided. Example substrates for vertical surface mount to a motherboard have multi-surface edge pads. The vertical mount substrates may be those of a laminate-based FlipNAND. The multi-surface edge pads have cutouts or recesses that expose more surfaces and more surface area of the substrate for bonding with the motherboard. The cutouts in the edge pads allow more solder to be used between the attachment surface of the substrate and the motherboard. The placement and geometry of the resulting solder joint is stronger and has less internal stress than conventional solder joints for vertical mounting. In an example process, blind holes can be drilled into a thickness of a substrate, and the blind holes plated with metal. The substrate can be cut in half though the plated holes to provide two substrates with plated multi-surface edge pads including the cutouts for mounting to the motherboard.