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公开(公告)号:US11069734B2
公开(公告)日:2021-07-20
申请号:US16513489
申请日:2019-07-16
申请人: Invensas Corporation
发明人: Rajesh Katkar
IPC分类号: H01L27/146 , H01L21/768 , H01L23/00 , H01L23/48
摘要: Methods of forming a back side image sensor device, as well as back side image sensor devices formed, are disclosed. In one such a method, an image sensor wafer having a first dielectric layer with a first surface is obtained. A reconstituted wafer having a processor die and a second dielectric layer with a second surface is obtained. The reconstituted wafer and the image sensor wafer are bonded to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer. In another method, such formation is for a processor die bonded to an image sensor wafer. In yet another method, such formation is for a processor die bonded to an image sensor die.
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公开(公告)号:US10802285B2
公开(公告)日:2020-10-13
申请号:US16292705
申请日:2019-03-05
申请人: Invensas Corporation
发明人: Belgacem Haba , Ilyas Mohammed , Rajesh Katkar
摘要: A virtual reality/augmented reality (VR/AR) headset system (including the capability for one or both of virtual reality and augmented reality) includes a remote optical engine. The remote disposition of the optical engine removes many or all of the components of the VR/AR headset system that add weight, heat, and other characteristics that can add to user discomfort in using the system from the headset. An electronic image is received and/or generated remotely at the optical engine, and is transmitted optically from the remote location to the headset to be viewed by the user. One or more optical waveguides may be used to transmit the electronic image to one or more passive displays of the headset, from the remote optical engine.
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公开(公告)号:US10593563B2
公开(公告)日:2020-03-17
申请号:US15873218
申请日:2018-01-17
申请人: Invensas Corporation
发明人: Belgacem Haba , Ilyas Mohammed , Rajesh Katkar
IPC分类号: H01L21/48 , H01L21/56 , H01L21/78 , H01L23/538 , H01L25/10 , H01L23/00 , H01L23/498 , H01L21/683 , H01L23/31
摘要: Fan-out wafer level packages with resist vias are provided. In an implementation, an example wafer level process or panel fabrication process includes adhering a die to a carrier, applying a temporary resist layer over the die and the carrier, developing the resist layer to form channels or spaces, filling the channels or the spaces with a molding material, removing the remaining resist to create vias in the molding material, and metalizing the vias in the molding material to provide conductive vias for the microelectronics package. The methods automatically create good via and pad alignment. In another implementation, an example process includes adhering a die to a carrier, applying a permanent resist layer over the die and the carrier, developing the resist layer to form vias in the resist layer, and metalizing the vias in the remaining resist of the permanent resist layer to provide conductive vias for the microelectronics package. Assemblies may be constructed with the semiconductor dies face-up or face-down. One or more redistribution layers (RDLs) may be built on one or both sides of an assembly with resist vias.
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公开(公告)号:US10354945B2
公开(公告)日:2019-07-16
申请号:US15660718
申请日:2017-07-26
申请人: Invensas Corporation
发明人: Rajesh Katkar , Min Tao , Javier A. Delacruz , Hoki Kim , Akash Agrawal
IPC分类号: H05K1/11 , H05K1/14 , H05K1/18 , H05K3/34 , H05K3/36 , H01L21/48 , H01L23/00 , H01L23/13 , H01L25/10 , H01L23/498
摘要: Multi-surface edge pads for vertical mount packages and methods of making package stacks are provided. Example substrates for vertical surface mount to a motherboard have multi-surface edge pads. The vertical mount substrates may be those of a laminate-based FlipNAND. The multi-surface edge pads have cutouts or recesses that expose more surfaces and more surface area of the substrate for bonding with the motherboard. The cutouts in the edge pads allow more solder to be used between the attachment surface of the substrate and the motherboard. The placement and geometry of the resulting solder joint is stronger and has less internal stress than conventional solder joints for vertical mounting. In an example process, blind holes can be drilled into a thickness of a substrate, and the blind holes plated with metal. The substrate can be cut in half though the plated holes to provide two substrates with plated multi-surface edge pads including the cutouts for mounting to the motherboard.
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公开(公告)号:US20190172903A1
公开(公告)日:2019-06-06
申请号:US16272736
申请日:2019-02-11
申请人: Invensas Corporation
发明人: Liang Wang , Hong Shen , Rajesh Katkar
IPC分类号: H01L49/02 , H01L23/00 , H01L21/56 , H01L23/522 , H01L25/00 , H01L25/16 , H01L25/11 , H01L25/10 , H01L23/498
CPC分类号: H01L28/60 , H01L21/4853 , H01L21/486 , H01L21/56 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L23/5223 , H01L24/05 , H01L24/32 , H01L24/83 , H01L25/105 , H01L25/11 , H01L25/115 , H01L25/165 , H01L25/50 , H01L28/40 , H01L28/65 , H01L2224/05009 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/1205 , H01L2924/15311 , H01L2924/16153 , H01L2924/00
摘要: Each of a first and a second integrated circuit structures has hole(s) in the top surface, and capacitors at least partially located in the holes. A semiconductor die is attached to the top surface of the second structure. Then the first and second structures are bonded together so that the die becomes disposed in the first structure's cavity, and the holes of the two structures are aligned to electrically connect the respective capacitors to each other. A filler is injected into the cavity through one or more channels in the substrate of the first structure. Other embodiments are also provided.
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公开(公告)号:US20190148339A1
公开(公告)日:2019-05-16
申请号:US16246863
申请日:2019-01-14
申请人: Invensas Corporation
发明人: Liang Wang , Rajesh Katkar
IPC分类号: H01L25/065 , H01L23/31 , H01L25/00 , H01L21/56 , H01L21/768 , H01L23/00
CPC分类号: H01L25/0652 , H01L21/561 , H01L21/566 , H01L21/568 , H01L21/76877 , H01L23/3114 , H01L23/3128 , H01L23/3135 , H01L24/05 , H01L24/08 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/82 , H01L24/96 , H01L25/0655 , H01L25/16 , H01L25/50 , H01L2224/04105 , H01L2224/08145 , H01L2224/12105 , H01L2224/16145 , H01L2224/24145 , H01L2224/73209 , H01L2224/73253 , H01L2224/821 , H01L2224/92124 , H01L2224/96 , H01L2224/97 , H01L2225/06527 , H01L2225/06548 , H01L2225/06562 , H01L2225/06586 , H01L2924/14 , H01L2924/18161 , H01L2924/18162 , H01L2224/80001 , H01L2224/81
摘要: Apparatuses and methods are described. This apparatus includes a bridge die having first contacts on a die surface being in a molding layer of a reconstituted wafer. The reconstituted wafer has a wafer surface including a layer surface of the molding layer and the die surface. A redistribution layer on the wafer surface includes electrically conductive and dielectric layers to provide conductive routing and conductors. The conductors extend away from the die surface and are respectively coupled to the first contacts at bottom ends thereof. At least second and third IC dies respectively having second contacts on corresponding die surfaces thereof are interconnected to the bridge die and the redistribution layer. A first portion of the second contacts are interconnected to top ends of the conductors opposite the bottom ends thereof in part for alignment of the at least second and third IC dies to the bridge die.
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公开(公告)号:US20190088607A1
公开(公告)日:2019-03-21
申请号:US16196313
申请日:2018-11-20
申请人: Invensas Corporation
发明人: Liang Wang , Rajesh Katkar , Hong Shen
IPC分类号: H01L23/00 , H01L25/065 , H01L25/10 , H01L23/34 , H01L23/31 , H01L23/498 , H01L23/367 , H01L25/18 , B81B7/00 , H01L23/538 , H01L21/56 , H01L25/00 , H01L23/48 , H01L21/768 , B81C1/00
摘要: In a multi-chip module (MCM), a “super” chip (110N) is attached to multiple “plain” chips (110F′ “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (110F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.
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公开(公告)号:US10204977B2
公开(公告)日:2019-02-12
申请号:US15804847
申请日:2017-11-06
申请人: INVENSAS CORPORATION
发明人: Liang Wang , Hong Shen , Rajesh Katkar
IPC分类号: H01L21/56 , H01L49/02 , H01L23/00 , H01L25/10 , H01L25/11 , H01L25/16 , H01L25/00 , H01L23/498 , H01L23/522
摘要: Each of a first and a second integrated circuit structures has hole(s) in the top surface, and capacitors at least partially located in the holes. A semiconductor die is attached to the top surface of the second structure. Then the first and second structures are bonded together so that the die becomes disposed in the first structure's cavity, and the holes of the two structures are aligned to electrically connect the respective capacitors to each other. A filler is injected into the cavity through one or more channels in the substrate of the first structure. Other embodiments are also provided.
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公开(公告)号:US20180366392A1
公开(公告)日:2018-12-20
申请号:US16037519
申请日:2018-07-17
申请人: Invensas Corporation
发明人: Rajesh Katkar , Cyprian Emeka Uzoh
IPC分类号: H01L23/48 , H01L23/498 , H01L21/48 , H01L21/768
CPC分类号: H01L23/481 , H01L21/481 , H01L21/4853 , H01L21/486 , H01L21/4889 , H01L21/6835 , H01L21/76898 , H01L23/3731 , H01L23/3738 , H01L23/49827 , H01L24/43 , H01L24/46 , H01L2221/68345 , H01L2221/68359 , H01L2224/023 , H01L2224/4502 , H01L2924/00014 , H01L2924/15311 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A component such as an interposer or microelectronic element can be fabricated with a set of vertically extending interconnects of wire bond structure. Such method may include forming a structure having wire bonds extending in an axial direction within one of more openings in an element and each wire bond spaced at least partially apart from a wall of the opening within which it extends, the element consisting essentially of a material having a coefficient of thermal expansion (“CTE”) of less than 10 parts per million per degree Celsius (“ppm/° C.”). First contacts can then be provided at a first surface of the component and second contacts provided at a second surface of the component facing in a direction opposite from the first surface, the first contacts electrically coupled with the second contacts through the wire bonds.
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公开(公告)号:US20180301436A1
公开(公告)日:2018-10-18
申请号:US16008531
申请日:2018-06-14
申请人: Invensas Corporation
发明人: Cyprian Emeka Uzoh , Rajesh Katkar
IPC分类号: H01L25/065 , H01L49/02 , B81B7/00 , H01L25/00 , H01L25/16 , H01L23/00 , H01L23/538 , H01L23/522 , H01L23/498 , H01L23/48 , H01L23/42 , H01L23/367 , H01L21/48
CPC分类号: H01L25/0657 , B81B7/0074 , H01L21/4853 , H01L23/3675 , H01L23/42 , H01L23/481 , H01L23/49811 , H01L23/522 , H01L23/5383 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/24 , H01L24/32 , H01L24/33 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L25/16 , H01L25/50 , H01L28/10 , H01L28/20 , H01L28/40 , H01L2224/0239 , H01L2224/0332 , H01L2224/0333 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/03614 , H01L2224/0391 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/04042 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05169 , H01L2224/05184 , H01L2224/05547 , H01L2224/05565 , H01L2224/05568 , H01L2224/05569 , H01L2224/05611 , H01L2224/05616 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05669 , H01L2224/05684 , H01L2224/1134 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11903 , H01L2224/1191 , H01L2224/13022 , H01L2224/13023 , H01L2224/13025 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/13184 , H01L2224/13565 , H01L2224/13616 , H01L2224/1403 , H01L2224/14131 , H01L2224/14132 , H01L2224/14134 , H01L2224/16145 , H01L2224/16146 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/16265 , H01L2224/17181 , H01L2224/24147 , H01L2224/24227 , H01L2224/244 , H01L2224/32145 , H01L2224/3303 , H01L2224/33181 , H01L2224/45015 , H01L2224/45147 , H01L2224/48091 , H01L2224/48149 , H01L2224/4903 , H01L2224/73201 , H01L2224/73253 , H01L2224/73265 , H01L2224/81192 , H01L2224/81193 , H01L2224/81825 , H01L2224/94 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06562 , H01L2225/06568 , H01L2924/00014 , H01L2924/01074 , H01L2924/01082 , H01L2924/01322 , H01L2924/12042 , H01L2924/1205 , H01L2924/1206 , H01L2924/1207 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/16251 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/3841 , H01L2924/00 , H01L2924/01029 , H01L2924/014 , H01L2924/00012 , H01L2924/01028 , H01L2224/05 , H01L2224/13 , H01L2224/81 , H01L2224/45099
摘要: Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.
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