公开(公告)号：US20180331030A1

公开(公告)日：2018-11-15

申请号：US16041013

申请日：2018-07-20

申请人： Invensas Corporation

发明人： Cyprian Emeka Uzoh ,  Zhuowen Sun

IPC分类号： H01L23/522 ,  H01L23/498 ,  H01L23/48 ,  H01L21/768 ,  H01L21/48 ,  H01L23/14

CPC分类号： H01L23/5226 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/7682 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.

公开(公告)号：US09984992B2

公开(公告)日：2018-05-29

申请号：US14997774

申请日：2016-01-18

申请人： Invensas Corporation

发明人： Javier A. DeLaCruz ,  Abiola Awujoola ,  Ashok S. Prabhu ,  Christopher W. Lattin ,  Zhuowen Sun

IPC分类号： H05K1/02 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16

CPC分类号： H01L24/49 ,  H01L23/3121 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/17 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/11334 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17051 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48108 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H05K1/0284 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

摘要： In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.

公开(公告)号：US20180026019A1

公开(公告)日：2018-01-25

申请号：US15393112

申请日：2016-12-28

申请人： Invensas Corporation

发明人： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC分类号： H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

摘要： Package-on-package (“PoP”) devices with WLP (“WLP”) components with dual RDLs (“RDLs”) for surface mount dies and methods therefor. In a PoP, a first IC die surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region. A molding layer is formed over the upper surface of the package substrate. A first and a second WLP microelectronic component are located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. Each of the first and the second WLP microelectronic components have a second IC die located between a first RDL and a second RDL. A third and a fourth IC die are respectively surface mount coupled over the first and the second WLP microelectronic components.

公开(公告)号：US20180026017A1

公开(公告)日：2018-01-25

申请号：US15393068

申请日：2016-12-28

申请人： Invensas Corporation

发明人： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC分类号： H01L25/10 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L25/18

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

摘要： Dies-on-package devices and methods therefor are disclosed. In a dies-on-package device, a first IC die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with respect to the first IC die. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first IC die, and around bases and shafts of the conductive lines. A plurality of second IC dies is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. The plurality of second IC dies are respectively coupled to the sets of the conductive lines in middle third portions respectively of the plurality of second IC dies for corresponding fan-in regions thereof.

公开(公告)号：US20180026016A1

公开(公告)日：2018-01-25

申请号：US15393119

申请日：2016-12-28

申请人： Invensas Corporation

发明人： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC分类号： H01L25/07 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00 ,  H01L23/528 ,  H01L25/11

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

摘要： Package-on-package (“PoP”) devices with upper RDLs of WLP (“WLP”) components and methods therefor are disclosed. In a PoP device, a first IC die is surface mount coupled to an upper surface of the package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with reference to the first IC. A molding layer is formed over the upper surface of the package substrate. A first and a second WLP microelectronic component is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. Each of the first and the second WLP microelectronic components have a second IC die located below a first RDL respectively thereof. A third and a fourth IC die are respectively surface mount coupled over the first and the second WLP microelectronic components.

公开(公告)号：US09490222B1

公开(公告)日：2016-11-08

申请号：US14880967

申请日：2015-10-12

申请人： Invensas Corporation

发明人： Abiola Awujoola ,  Zhuowen Sun ,  Wael Zohni ,  Ashok S. Prabhu ,  Willmar Subido

IPC分类号： H01L23/552 ,  H01L23/00

CPC分类号： H01L23/552 ,  H01L23/49811 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/215 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4942 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73227 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05599

摘要： Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

摘要翻译： 公开了一般涉及具有防止干扰的微电子封装的装置。 在其装置中，基板具有与上表面相对的上表面和下表面，并具有接地平面。 第一微电子器件耦合到衬底的上表面。 引线接合线耦合到接地平面，用于对其进行干涉并延伸离开衬底的上表面。 引线接合线的第一部分被定位成相对于干涉为第一微电子器件提供屏蔽区域。 导线接合线的第二部分不定位成提供屏蔽区域。 第二微电子器件耦合到衬底并且位于屏蔽区域外部。 导电表面在用于覆盖屏蔽区域的引线接合线的第一部分之上。

公开(公告)号：US09460758B2

公开(公告)日：2016-10-04

申请号：US14753607

申请日：2015-06-29

申请人： Invensas Corporation

发明人： Richard Dewitt Crisp ,  Yong Chen ,  Belgacem Haba ,  Wael Zohni ,  Zhuowen Sun

IPC分类号： G11C5/00 ,  G11C5/02 ,  G11C5/06 ,  G11C8/00 ,  G11C8/16 ,  G11C8/18 ,  H01L23/00 ,  H01L25/065 ,  G11C5/04 ,  G11C8/12 ,  G11C11/408 ,  H01L23/538 ,  H01L25/10

CPC分类号： G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C8/12 ,  G11C11/408 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

摘要： A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements.

公开(公告)号：US20160093563A1

公开(公告)日：2016-03-31

申请号：US14497825

申请日：2014-09-26

申请人： INVENSAS CORPORATION

发明人： Yong Chen ,  Zhuowen Sun ,  Kyong-Mo Bang

IPC分类号： H01L23/498 ,  H05K1/02

CPC分类号： H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/181 ,  H05K1/0262 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09336 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A microelectronic package can include a substrate and a microelectronic element. The substrate can include terminals comprising at least first power terminals and other terminals in an area array at a surface of the substrate. The substrate can also include a power plane element electrically coupled to the first power terminals. The area array can have a peripheral edge and a continuous gap between the terminals extending inwardly from the peripheral edge in a direction parallel to the surface. The terminals on opposite sides of the gap can be spaced from one another by at least 1.5 times a minimum pitch of the terminals. The power plane element can extend within the gap from at least the peripheral edge at least to the first power terminals. Each first power terminal can be separated from the peripheral edge by two or more of the other terminals.

摘要翻译： 微电子封装可以包括衬底和微电子元件。 衬底可以包括在衬底的表面处的区域阵列中至少包括第一电源端子和其他端子的端子。 基板还可以包括电耦合到第一电源端子的功率平面元件。 区域阵列可以具有周边边缘和在平行于表面的方向上从周边边缘向内延伸的端子之间的连续间隙。 间隙的相对侧上的端子可以彼此间隔开至少1.5倍的端子的最小间距。 功率平面元件可以在间隙内从至少外围边缘至少延伸到第一电源端子。 每个第一电源端子可以通过两个或更多其它端子与外围边缘分离。

公开(公告)号：US20160093340A1

公开(公告)日：2016-03-31

申请号：US14496159

申请日：2014-09-25

申请人： Invensas Corporation

发明人： Zhuowen Sun ,  Yong Chen

IPC分类号： G11C5/06 ,  G11C5/02

CPC分类号： G11C5/063 ,  G11C5/025 ,  H01L24/00

摘要： A microelectronic package has terminals at a surface of a substrate having first and second half areas, each half area extending from a diagonal that bisects the first surface and a respective opposite corner of the first surface. Terminals for carrying data and address information in the first half area provide first memory channel access to a first memory storage array, and terminals for carrying data and address information in the second half area provide second memory channel access to a second memory storage array. The package may include first and second microelectronic elements overlying a same surface of the substrate which may be stacked in transverse orientations.

摘要翻译： 微电子封装在具有第一和第二半区域的衬底的表面上具有端子，每个半区域从对角线延伸，该对角线将第一表面和第一表面的相应的相对角分成两部分。 用于承载前半部分中的数据和地址信息的终端提供对第一存储器存储阵列的第一存储器通道访问，并且用于承载第二半部分中的数据和地址信息的终端提供对第二存储器存储阵列的第二存储器通道访问。 封装可以包括覆盖在基板的相同表面上的第一和第二微电子元件，其可以以横向取向堆叠。

公开(公告)号：US09281296B2

公开(公告)日：2016-03-08

申请号：US14448040

申请日：2014-07-31

申请人： Invensas Corporation

发明人： Zhuowen Sun ,  Yong Chen ,  Kyong-Mo Bang

IPC分类号： H01L25/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/481 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00015

摘要： A microelectronic package can include a substrate comprising a dielectric element having first and second opposite surfaces, and a microelectronic element having a face extending parallel to the first surface. The substrate can also include a plurality of peripheral edges extending between the first and second surfaces defining a generally rectangular or square periphery of the substrate. The substrate can further include a plurality of contacts and terminals, the contacts being at the first surface, the terminals being at at least one of the first or second surfaces. The microelectronic elements can have a plurality of edges bounding the face, and a plurality of element contacts at the face electrically coupled with the terminals through the contacts of the substrate. Each edge of the microelectronic element can be oriented at an oblique angle with respect to the peripheral edges of the substrate.

摘要翻译： 微电子封装可以包括包括具有第一和第二相对表面的电介质元件的基板和具有平行于第一表面延伸的面的微电子元件。 衬底还可以包括在第一和第二表面之间延伸的多个外围边缘，其限定基底的大致矩形或正方形的周边。 所述基板还可包括多个触点和端子，所述触点位于所述第一表面处，所述端子处于所述第一或第二表面中的至少一个。 微电子元件可以具有限定该面的多个边缘，并且在该表面处的多个元件触点通过基板的触点与端子电耦合。 微电子元件的每个边缘可以相对于衬底的周边边缘倾斜地定向。