公开(公告)号：US07554147B2

公开(公告)日：2009-06-30

申请号：US11374074

申请日：2006-03-14

申请人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai ,  Yukio Fuji ,  Kazuhiko Kajigaya

发明人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai ,  Yukio Fuji ,  Kazuhiko Kajigaya

IPC分类号： H01L27/108

CPC分类号： G11C13/0004 ,  G11C11/005 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

摘要： A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line and the PCRAM bit line. The memory device further has a capacitive element disposed on the upper layer of the DRAM bit line, and a phase-change element disposed on the upper layer of the PCRAM bit line. The lower electrode of the capacitive element and the lower electrode of the phase-change memory element are formed on the shared conductive layer.

摘要翻译： 其中安装了DRAM和相变存储器（PCRAM）的存储器件具有形成在与DRAM位线共享的导电层上的DRAM位线，PCRAM位线或PCRAM源线，以及读出放大器 连接在DRAM位线和PCRAM位线之间。 存储器件还具有设置在DRAM位线的上层上的电容元件和设置在PCRAM位线的上层上的相变元件。 电容元件的下电极和相变存储元件的下电极形成在共用导电层上。

公开(公告)号：US20060211231A1

公开(公告)日：2006-09-21

申请号：US11374074

申请日：2006-03-14

申请人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai ,  Yukio Fuji ,  Kazuhiko Kajigaya

发明人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai ,  Yukio Fuji ,  Kazuhiko Kajigaya

IPC分类号： H01L21/3205

CPC分类号： G11C13/0004 ,  G11C11/005 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

摘要： A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line and the PCRAM bit line. The memory device further has a capacitive element disposed on the upper layer of the DRAM bit line, and a phase-change element disposed on the upper layer of the PCRAM bit line. The lower electrode of the capacitive element and the lower electrode of the phase-change memory element are formed on the shared conductive layer.

公开(公告)号：US07449711B2

公开(公告)日：2008-11-11

申请号：US11329224

申请日：2006-01-11

申请人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Yukio Fuji ,  Kiyoshi Nakai ,  Kazuhiko Kajigaya

发明人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Yukio Fuji ,  Kiyoshi Nakai ,  Kazuhiko Kajigaya

IPC分类号： H01L47/00

CPC分类号： H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： A phase-change memory device includes a plurality of bit lines extending in a row direction, a plurality of selection lines extending in a column direction, and an array of memory cells each disposed at one of intersections between the bit lines and selection lines. Each memory cell includes a chalcogenide element and a diode connected in series, and an n-type contact layer underlying the n-type layer of the diode. Adjacent two of memory cells share a common bit-line contact plug connecting the n-type contact layers and the bit line.

摘要翻译： 相变存储器件包括沿行方向延伸的多个位线，沿列方向延伸的多条选择线，以及各自设置在位线和选择线之间的交叉点之一处的存储单元阵列。 每个存储单元包括串联的硫族化物元件和二极管，以及二极管的n型层下面的n型接触层。 相邻的两个存储单元共享连接n型接触层和位线的公共位线接触插头。

公开(公告)号：US20060151771A1

公开(公告)日：2006-07-13

申请号：US11329224

申请日：2006-01-11

申请人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Yukio Fuji ,  Kiyoshi Nakai ,  Kazuhiko Kajigaya

发明人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Yukio Fuji ,  Kiyoshi Nakai ,  Kazuhiko Kajigaya

IPC分类号： H01L29/02

CPC分类号： H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： A phase-change memory device includes a plurality of bit lines extending in a row direction, a plurality of selection lines extending in a column direction, and an array of memory cells each disposed at one of intersections between the bit lines and selection lines. Each memory cell includes a chalcogenide element and a diode connected in series, and an n-type contact layer underlying the n-type layer of the diode. Adjacent two of memory cells share a common bit-line contact plug connecting the n-type contact layers and the bit line.

摘要翻译： 相变存储器件包括沿行方向延伸的多个位线，沿列方向延伸的多条选择线，以及各自设置在位线和选择线之间的交叉点之一处的存储单元阵列。 每个存储单元包括串联的硫族化物元件和二极管，以及二极管的n型层下面的n型接触层。 相邻的两个存储单元共享连接n型接触层和位线的公共位线接触插头。

公开(公告)号：US20080043522A1

公开(公告)日：2008-02-21

申请号：US11666160

申请日：2005-10-25

申请人： Yukio Fuji ,  Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai

发明人： Yukio Fuji ,  Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C2213/78 ,  H01L27/0207 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： For the purpose of providing a phase change memory device advantageous in layout and operation control by obtaining sufficient write current for high integrated phase change memory devices, the nonvolatile semiconductor memory device of the invention in which word lines and bit lines are arranged in a matrix-shape comprises a select transistor formed at each cross point of the word lines and the bit lines, and a plurality of memory elements commonly connected to the select transistor at one end and connected to a different element select line at an other end and which is capable of writing and reading data. Write and read operations for the selected memory element are controlled by supplying a predetermined current through the select transistor and through the element select line connected to the selected memory element, and the element select lines are arranged in parallel with the bit lines.

摘要翻译： 为了通过获得用于高集成相变存储器件的足够的写入电流来提供有利于布局和操作控制的相变存储器件，本发明的非易失性半导体存储器件，其中字线和位线被布置成矩阵型， 形状包括形成在字线和位线的每个交叉点处的选择晶体管，以及多个存储元件，其一端共同连接到选择晶体管，并且在另一端连接到不同的元件选择线，并且能够 写和读数据。 通过提供预定电流通过选择晶体管并通过连接到所选择的存储元件的元件选择线来控制所选存储元件的写和读操作，并且元件选择线与位线并联布置。

公开(公告)号：US20060176724A1

公开(公告)日：2006-08-10

申请号：US11349959

申请日：2006-02-09

申请人： Isamu Asano ,  Yukio Fuji ,  Kiyoshi Nakai ,  Tsuyoshi Kawagoe

发明人： Isamu Asano ,  Yukio Fuji ,  Kiyoshi Nakai ,  Tsuyoshi Kawagoe

IPC分类号： G11C17/06

CPC分类号： G11C13/0004 ,  G11C13/003 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： A phase change memory device, comprising a phase change memory device; a semiconductor substrate; a MOS transistor disposed at each intersection of a plurality of word lines and a plurality of bit lines arranged in a matrix form; a plurality of phase change memory elements for storing data of a plurality of bits, each formed on an upper area opposite to a diffusion layer of the MOS transistor in a phase change layer made of phase change material; a lower electrode structure for electrically connecting each of the plurality of phase change memory elements to the diffusion layer of the MOS transistor.

摘要翻译： 一种相变存储器件，包括相变存储器件; 半导体衬底; 设置在多个字线和以矩阵形式布置的多个位线的交点处的MOS晶体管; 多个相变存储元件，用于存储多个位的数据，各自形成在由相变材料制成的相变层中的与MOS晶体管的扩散层相反的上部区域上; 用于将多个相变存储元件中的每一个电连接到MOS晶体管的扩散层的下电极结构。

公开(公告)号：US07502252B2

公开(公告)日：2009-03-10

申请号：US11666160

申请日：2005-10-25

申请人： Yukio Fuji ,  Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai

发明人： Yukio Fuji ,  Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C2213/78 ,  H01L27/0207 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： For the purpose of providing a phase change memory device advantageous in layout and operation control by obtaining sufficient write current for high integrated phase change memory devices, the nonvolatile semiconductor memory device of the invention in which word lines and bit lines are arranged in a matrix-shape comprises a select transistor formed at each cross point of the word lines and the bit lines, and a plurality of memory elements commonly connected to the select transistor at one end and connected to a different element select line at an other end and which is capable of writing and reading data. Write and read operations for the selected memory element are controlled by supplying a predetermined current through the select transistor and through the element select line connected to the selected memory element, and the element select lines are arranged in parallel with the bit lines.

摘要翻译： 为了通过获得用于高集成相变存储器件的足够的写入电流来提供有利于布局和操作控制的相变存储器件，本发明的非易失性半导体存储器件，其中字线和位线被布置成矩阵型， 形状包括形成在字线和位线的每个交叉点处的选择晶体管，以及多个存储元件，其一端共同连接到选择晶体管，并且在另一端连接到不同的元件选择线，并且能够 写和读数据。 通过提供预定电流通过选择晶体管并通过连接到所选择的存储元件的元件选择线来控制所选存储元件的写和读操作，并且元件选择线与位线并联布置。

公开(公告)号：US07675770B2

公开(公告)日：2010-03-09

申请号：US11349959

申请日：2006-02-09

申请人： Isamu Asano ,  Yukio Fuji ,  Kiyoshi Nakai ,  Tsuyoshi Kawagoe

发明人： Isamu Asano ,  Yukio Fuji ,  Kiyoshi Nakai ,  Tsuyoshi Kawagoe

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/003 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： A phase change memory device, comprising a phase change memory device; a semiconductor substrate; a MOS transistor disposed at each intersection of a plurality of word lines and a plurality of bit lines arranged in a matrix form; a plurality of phase change memory elements for storing data of a plurality of bits, each formed on an upper area opposite to a diffusion layer of the MOS transistor in a phase change layer made of phase change material; a lower electrode structure for electrically connecting each of the plurality of phase change memory elements to the diffusion layer of the MOS transistor.

摘要翻译： 一种相变存储器件，包括相变存储器件; 半导体衬底; 设置在多个字线和以矩阵形式布置的多个位线的交点处的MOS晶体管; 多个相变存储元件，用于存储多个位的数据，各自形成在由相变材料制成的相变层中的与MOS晶体管的扩散层相反的上部区域上; 用于将多个相变存储元件中的每一个电连接到MOS晶体管的扩散层的下电极结构。

公开(公告)号：US20070141786A1

公开(公告)日：2007-06-21

申请号：US11637069

申请日：2006-12-12

申请人： Tsuyoshi Kawagoe ,  Isamu Asano

发明人： Tsuyoshi Kawagoe ,  Isamu Asano

IPC分类号： H01L21/336

CPC分类号： H01L45/1658 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1625

摘要： A method of manufacturing a non-volatile memory element in the present invention comprises a first step for forming an adhesion layer on an interlayer insulating film so that an electrical connection is established with a lower electrode, a second step for forming a recording layer containing a phase change material on the adhesion layer, a third step for forming an upper electrode that is electrically connected to the recording layer, and a fourth step for diffusing in the recording layer some of the adhesion layer positioned between at least the lower electrode and the recording layer.

摘要翻译： 本发明的非易失性存储元件的制造方法包括：在层间绝缘膜上形成粘接层的第一工序，与下部电极形成电连接;第二工序，形成含有 形成与记录层电连接的上部电极的第三工序，以及在记录层中扩散位于至少下部电极与记录材料之间的一部分粘合层的第四工序 层。

公开(公告)号：US20120056148A1

公开(公告)日：2012-03-08

申请号：US13137687

申请日：2011-09-02

申请人： Tomoyasu Kakegawa ,  Isamu Asano ,  Tsuyoshi Kawagoe ,  Hiromi Sasaoka ,  Naoya Higano ,  Yuta Watanabe

发明人： Tomoyasu Kakegawa ,  Isamu Asano ,  Tsuyoshi Kawagoe ,  Hiromi Sasaoka ,  Naoya Higano ,  Yuta Watanabe

IPC分类号： H01L45/00

CPC分类号： H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1675

摘要： A semiconductor device may include, but is not limited to: a first insulating film; a second insulating film over the first insulating film; a first memory structure between the first and second insulating films; and a third insulating film between the first and second insulating films. The first memory structure may include, but is not limited to: a heater electrode; and a phase-change memory element between the heater electrode and the second insulating film. The phase-change memory element contacts the heater electrode. The third insulating film covers at least a side surface of the phase-change memory element. Empty space is positioned adjacent to at least one of the heater electrode and the third insulating film.

摘要翻译： 半导体器件可以包括但不限于：第一绝缘膜; 第一绝缘膜上的第二绝缘膜; 第一和第二绝缘膜之间的第一存储器结构; 以及在第一和第二绝缘膜之间的第三绝缘膜。 第一存储器结构可以包括但不限于：加热器电极; 以及加热器电极和第二绝缘膜之间的相变存储元件。 相变存储元件接触加热器电极。 第三绝缘膜覆盖相变存储元件的至少一个侧面。 空的空间位于与加热器电极和第三绝缘膜中的至少一个相邻的位置。