摘要:
A battery is charged by using in series a constant-voltage DC power supply with current limit function and a constant voltage circuit which has a differential comparator circuit and whose current limit value is variable. Following a period of charging with the current of current limit value by the constant-voltage DC power supply, a period is provided in correspondence with the state of charging of the battery, for charging with a current limit value of the constant voltage circuit which is smaller than that current limit value. The detection of the charging state of the battery is effected by a comparison between a current value of a current source of a differential comparator circuit and a differential output of that differential comparator circuit. It enables to reduce electric power consumed by the control transistor of the constant voltage circuit and to reduce the allowable loss required for the control transistor.
摘要:
A detection circuit is mounted on an electronic device having a communication function, including at least a battery, a CPU, and a communication unit, and is configured to detect the remaining battery charge. An A/D converter performs sampling of a magnitude of a current IBAT discharged from the battery, and converts the current IBAT thus sampled into a digital current value. An interface circuit receives, from the CPU, control data which indicates a period in which there is an increase in the current discharged from the battery. Based upon the control data, a control unit raises the sampling frequency of the A/D converter in the period in which there is an increase in the current IBAT.
摘要翻译:检测电路安装在具有通信功能的电子设备上,至少包括电池,CPU和通信单元,并且被配置为检测剩余电池电量。 A / D转换器对从电池放电的电流IBAT的大小进行采样,并将由此采样的电流IBAT转换为数字电流值。 接口电路从CPU接收指示从电池释放的电流增加的期间的控制数据。 基于控制数据,控制单元在当前IBAT增加的时段内提高A / D转换器的采样频率。
摘要:
A pulse generating unit receives a clock at a predetermined frequency, and generates a pulse signal which transits synchronously with the positive edge of the clock. A flip-flop acquires the pulse signal every time a positive edge occurs in an inverted clock output from the inverter. A logic gate multiplexes the pulse signal and the output of the flip-flop. A selector selects either the output of the logic gate or the pulse signal.