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15 条记录 (耗时 0.028 秒)

    DATA OUTPUT BUFFER AND MEMORY DEVICE
    4.
    发明申请
    DATA OUTPUT BUFFER AND MEMORY DEVICE 有权
    数据输出缓冲器和存储器件

    公开(公告)号：US20120099383A1

    公开(公告)日：2012-04-26

    申请号：US13239478

    申请日：2011-09-22

    申请人： Si-Hong Kim ,  Seung-Jun Bae ,  Jin-Il Lee ,  Kwang-Il Park

    发明人： Si-Hong Kim ,  Seung-Jun Bae ,  Jin-Il Lee ,  Kwang-Il Park

    IPC分类号： G11C7/00 ,  G11C7/10

    CPC分类号： G11C7/1057 ,  G11C29/022 ,  G11C29/028 ,  G11C2207/2254

    摘要： A data output buffer includes a driving unit and a control unit. The driving unit selectively performs a termination operation that provides a termination impedance to a transmission line coupled to an external pin, and a driving operation that provides a drive impedance to the transmission line while outputting read data. The control unit adjusts a value of the termination impedance and a value of the drive impedance based on an output voltage at the external pin during a termination mode, and controls the driving unit to selectively perform one of the termination operation and the driving operation during a driving mode.

    摘要翻译： 数据输出缓冲器包括驱动单元和控制单元。 驱动单元选择性地执行向耦合到外部引脚的传输线提供终止阻抗的终止操作，以及在输出读取数据的同时向传输线提供驱动阻抗的驱动操作。 控制单元在终端模式期间根据外部引脚的输出电压来调整终端阻抗的值和驱动阻抗的值，并且控制驱动单元选择性地执行终止操作和驱动操作之一 驾驶模式。

    Data output buffer and memory device
    6.
    发明授权
    Data output buffer and memory device 有权
    数据输出缓冲器和存储器件

    公开(公告)号：US08553471B2

    公开(公告)日：2013-10-08

    申请号：US13239478

    申请日：2011-09-22

    申请人： Si-Hong Kim ,  Seung-Jun Bae ,  Jin-Il Lee ,  Kwang-Il Park

    发明人： Si-Hong Kim ,  Seung-Jun Bae ,  Jin-Il Lee ,  Kwang-Il Park

    IPC分类号： G11C7/10 ,  G11C7/00

    CPC分类号： G11C7/1057 ,  G11C29/022 ,  G11C29/028 ,  G11C2207/2254

    摘要： A data output buffer includes a driving unit and a control unit. The driving unit selectively performs a termination operation that provides a termination impedance to a transmission line coupled to an external pin, and a driving operation that provides a drive impedance to the transmission line while outputting read data. The control unit adjusts a value of the termination impedance and a value of the drive impedance based on an output voltage at the external pin during a termination mode, and controls the driving unit to selectively perform one of the termination operation and the driving operation during a driving mode.

    摘要翻译： 数据输出缓冲器包括驱动单元和控制单元。 驱动单元选择性地执行向耦合到外部引脚的传输线提供终止阻抗的终止操作，以及在输出读取数据的同时向传输线提供驱动阻抗的驱动操作。 控制单元在终端模式期间根据外部引脚的输出电压来调整终端阻抗的值和驱动阻抗的值，并且控制驱动单元选择性地执行终止操作和驱动操作之一 驾驶模式。

    Apparatus and method for latency control in high frequency synchronous semiconductor device
    7.
    发明授权
    Apparatus and method for latency control in high frequency synchronous semiconductor device 有权
    高频同步半导体器件中等待时间控制的装置和方法

    公开(公告)号：US08988126B2

    公开(公告)日：2015-03-24

    申请号：US11198596

    申请日：2005-08-04

    申请人： Si-Hong Kim ,  Sang-Sic Yoon

    发明人： Si-Hong Kim ,  Sang-Sic Yoon

    IPC分类号： G06F1/04 ,  G11C29/02 ,  G11C7/22 ,  G11C11/4076 ,  G11C29/50

    CPC分类号： G11C29/023 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/50012

    摘要： An apparatus for controlling a latency in a synchronous semiconductor device. The apparatus includes a first counting block for counting a cycle of a first clock signal to thereby generate a first binary code; a second counting block for counting a cycle of a second clock signal to thereby generate a second binary code. The second clock signal is obtained by delaying the first clock signal by a predetermined delay amount, A code comparison block stores the second binary code in response to a command and compares the first binary code with the second binary code to thereby generate a latency control signal.

    摘要翻译： 一种用于控制同步半导体器件中的等待时间的装置。 该装置包括：第一计数块，用于对第一时钟信号的周期进行计数，从而生成第一二进制码; 第二计数块，用于对第二时钟信号的周期进行计数，从而生成第二二进制码。 通过将第一时钟信号延迟预定的延迟量来获得第二时钟信号，A代码比较块响应于命令存储第二二进制码，并将第一二进制码与第二二进制码进行比较，从而生成等待时间控制信号 。

    Delay locked loop DLL in semiconductor device
    8.
    发明授权
    Delay locked loop DLL in semiconductor device 有权
    半导体器件中延迟锁定环DLL

    公开(公告)号：US06693474B2

    公开(公告)日：2004-02-17

    申请号：US10331338

    申请日：2002-12-31

    申请人： Si-Hong Kim

    发明人： Si-Hong Kim

    IPC分类号： H03L706

    CPC分类号： H03L7/0812

    摘要： A semiconductor device has a DLL circuit for generating an internal clock signal by receiving an external clock signal, wherein the DLL circuit includes a delay model for modeling delay time of an intern clock signal delayed from an external clock signal and a power supply for adjusting a core voltage by an input output voltage and supplying the adjusted voltage to the delay model.

    摘要翻译： 半导体器件具有用于通过接收外部时钟信号来产生内部时钟信号的DLL电路，其中所述DLL电路包括延迟模型，用于建模从外部时钟信号延迟的实时时钟信号的延迟时间和用于调整外部时钟信号的电源 通过输入输出电压提供核心电压，并将调整后的电压提供给延迟模型。

    SEMICONDUCTOR DEVICE CAPABLE OF TESTING A TRANSMISSION LINE FOR AN IMPEDANCE CALIBRATION CODE
    9.
    发明申请
    SEMICONDUCTOR DEVICE CAPABLE OF TESTING A TRANSMISSION LINE FOR AN IMPEDANCE CALIBRATION CODE 有权
    用于测试用于阻抗校准码的传输线的半导体器件

    公开(公告)号：US20100237902A1

    公开(公告)日：2010-09-23

    申请号：US12719953

    申请日：2010-03-09

    申请人： Young-Hoon Sohn ,  Kwang-Il Park ,  Yong-Gwon Jeong ,  Si-Hong Kim

    发明人： Young-Hoon Sohn ,  Kwang-Il Park ,  Yong-Gwon Jeong ,  Si-Hong Kim

    IPC分类号： H03K19/003 ,  G01R35/00

    CPC分类号： H04L25/0278

    摘要： A semiconductor device includes a plurality of pads, where an external reference resistor is connected to a first one of the pads, an impedance calibrating unit configured to generate an impedance calibration code corresponding to an impedance of the reference resistor and output the impedance calibration code to a code transmitting line during a normal operating mode, and an impedance matching unit configured to perform an impedance matching operation in response to the impedance calibration code during the normal operating mode. The impedance calibrating unit is configured to output a test code to the code transmitting line in response to a test signal during a test operating mode. The impedance matching unit is configured to serialize the test code to output the serialized test code to each of the other pads in response to the test signal during the test operating mode.

    摘要翻译： 半导体器件包括多个焊盘，其中外部参考电阻器连接到焊盘的第一焊盘，阻抗校准单元被配置为产生对应于参考电阻器的阻抗的阻抗校准代码，并将阻抗校准代码输出到 在正常操作模式期间的代码传输线，以及阻抗匹配单元，被配置为在正常操作模式期间响应于阻抗校准码执行阻抗匹配操作。 阻抗校准单元被配置为在测试操作模式期间响应于测试信号将测试代码输出到代码传输线。 阻抗匹配单元被配置为串行化测试代码，以在测试操作模式期间响应于测试信号将串行测试代码输出到每个其它焊盘。