公开(公告)号：US08031009B2

公开(公告)日：2011-10-04

申请号：US12581105

申请日：2009-10-16

申请人： Byung Hun Min ,  Ja Yol Lee ,  Seong Do Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu

发明人： Byung Hun Min ,  Ja Yol Lee ,  Seong Do Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu

IPC分类号： H03L7/085 ,  H03L7/095 ,  H03L7/18 ,  H03L7/081

CPC分类号： H03L7/181 ,  H03L2207/50 ,  Y10S331/02

摘要： A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting an oscillation frequency of an oscillation signal according to a control value; a programmable divider dividing the oscillation signal according to a division ratio to output a divided signal; a counter counting the number of clocks of the divided signal for one cycle of a reference signal to output a count value; and a frequency detector obtaining the control value by subtracting the count value from a reference comparison value, wherein the reference comparison value is obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider.

摘要翻译： 一种频率校准环路电路，具有预定的频道字（FCW）指令值，为了获得振荡器中的目标频率输入的比特和可编程分频器的预设最小分频比n（n是常数） 包括：振荡器，根据控制值调整振荡信号的振荡频率; 可编程分频器，根据分频比除以振荡信号，输出分频信号; 计数针对参考信号的一个周期的分频信号的时钟数，以输出计数值; 以及频率检测器，通过从参考比较值中减去计数值来获得控制值，其中通过将频率通道字（FCW）指令值除以可编程分频器的最小分频比来获得参考比较值。

公开(公告)号：US20100134195A1

公开(公告)日：2010-06-03

申请号：US12629742

申请日：2009-12-02

申请人： Ja Yol LEE ,  Byung Hun Min ,  Seong Do Kim ,  Hyun Kyu Yu

发明人： Ja Yol LEE ,  Byung Hun Min ,  Seong Do Kim ,  Hyun Kyu Yu

IPC分类号： H03B5/12 ,  H01L27/06

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/1265

摘要： There is provided a capacitor having variable capacitance, which forms different capacitances according to a control signal by applying a switch to a metal-oxide-metal (MOM) structure plate capacitor using a CMOS process. The capacitor includes a stack structure including a plurality of metal layers including a first metal layer, and a plurality of dielectric layers respectively interposed between the plurality of metal layers, and a switch part including at least one switch having one side connected to at least one metal layer among the plurality of metal layers other than the first metal layer. The first metal layer and the other side of the switch serve as both terminals of the capacitor, and at least two capacitances are provided between both terminals of the capacitor upon controlling a short/open of the switch.

摘要翻译： 提供具有可变电容的电容器，其通过使用CMOS工艺将开关施加到金属氧化物金属（MOM）结构板电容器上，根据控制信号形成不同的电容。 电容器包括堆叠结构，其包括多个金属层，包括第一金属层和分别介于多个金属层之间的多个电介质层，以及开关部分，其包括至少一个开关，该开关的一侧连接至至少一个 除了第一金属层之外的多个金属层中的金属层。 开关的第一金属层和另一侧用作电容器的两端，并且在控制开关的短路/断开时，至少两个电容设置在电容器的两个端子之间。

公开(公告)号：US07961038B2

公开(公告)日：2011-06-14

申请号：US12631637

申请日：2009-12-04

申请人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

发明人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

IPC分类号： H03B1/00

CPC分类号： G05B1/03

摘要： A digital proportional integral loop filter is provided. A first proportional amplification unit multiplies a phase error value by a first proportional loop gain, and a first integral amplification unit multiplies a phase error accumulation value by a first integral loop gain. A second proportional amplification unit multiplies the phase error value by a second proportional loop gain, and a second integral amplification unit multiplies the phase error accumulation value by a second integral loop gain. A first offset value generation unit generates a first offset value by subtracting the second proportional loop gain from the first proportional loop gain and multiplying a resulting value by a phase error average value, and a second offset value generation unit generates a second offset value by subtracting the second integral loop gain from the first integral loop gain and multiplying a resulting value by a phase error accumulation average value.

摘要翻译： 提供了数字比例积分环路滤波器。 第一比例放大单元将相位误差值乘以第一比例环路增益，并且第一积分放大单元将相位误差累积值乘以第一积分环路增益。 第二比例放大单元将相位误差值乘以第二比例环路增益，第二积分放大单元将相位误差累积值乘以第二积分环路增益。 第一偏移值生成单元通过从第一比例环增益中减去第二比例环增益并将结果值乘以相位误差平均值来生成第一偏移值，第二偏移值生成单元通过减去第二偏移值生成单位生成第二偏移值 来自第一积分环路增益的第二积分环路增益，并将得到的值乘以相位误差累积平均值。

公开(公告)号：US07999707B2

公开(公告)日：2011-08-16

申请号：US12629020

申请日：2009-12-01

申请人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

发明人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

IPC分类号： H03M1/06

CPC分类号： G04F10/06 ,  H03L7/085 ,  H03L2207/50

摘要： An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N−1)th fragmented delay phases; an adding unit adding each of the first to the (N−1)th fragmented delay phases to the phase error to generate first to (N−1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N−1)th phase errors.

摘要翻译： 公开了用于补偿时间 - 数字转换器（TDC）的误差的装置，以从包括TDC的相位检测器和包括TDC误差的相位误差接收延迟相位并补偿TDC误差以具有时间 分辨率提高N倍（N是自然数）。 该装置包括：分段和乘法单元，将延迟相位分片N次（N是自然数），以产生第一至第（N-1）个分段延迟相位; 加法单元将第一到第（N-1）个分段延迟相位中的每一个相加到相位误差，以产生第一到第（N-1）个相位误差; 以及比较单元从相位误差和第一到第（N-1）个相位误差获取最接近实际相位误差的相位误差补偿值。

公开(公告)号：US20100134335A1

公开(公告)日：2010-06-03

申请号：US12629020

申请日：2009-12-01

申请人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

发明人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

IPC分类号： H03M1/06

CPC分类号： G04F10/06 ,  H03L7/085 ,  H03L2207/50

摘要： An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N−1)th fragmented delay phases; an adding unit adding each of the first to the (N−1)th fragmented delay phases to the phase error to generate first to (N−1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N−1)th phase errors.

摘要翻译： 公开了用于补偿时间 - 数字转换器（TDC）的误差的装置，以从包括TDC的相位检测器和包括TDC误差的相位误差接收延迟相位并补偿TDC误差以具有时间 分辨率提高N倍（N是自然数）。 该装置包括：分段和乘法单元，将延迟相位分片N次（N是自然数），以产生第一到第（N-1）个分段延迟相位; 加法单元将第一到第（N-1）个分段延迟相位中的每一个相加到相位误差，以产生第一到第（N-1）个相位误差; 以及比较单元从相位误差和第一到第（N-1）个相位误差获取最接近实际相位误差的相位误差补偿值。

公开(公告)号：US20100145482A1

公开(公告)日：2010-06-10

申请号：US12631637

申请日：2009-12-04

申请人： Mi jeong PARK ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

发明人： Mi jeong PARK ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

IPC分类号： G05B13/02

CPC分类号： G05B1/03

摘要： A digital proportional integral loop filter is provided. A first proportional amplification unit multiplies a phase error value by a first proportional loop gain, and a first integral amplification unit multiplies a phase error accumulation value by a first integral loop gain. A second proportional amplification unit multiplies the phase error value by a second proportional loop gain, and a second integral amplification unit multiplies the phase error accumulation value by a second integral loop gain. A first offset value generation unit generates a first offset value by subtracting the second proportional loop gain from the first proportional loop gain and multiplying a resulting value by a phase error average value, and a second offset value generation unit generates a second offset value by subtracting the second integral loop gain from the first integral loop gain and multiplying a resulting value by a phase error accumulation average value.

摘要翻译： 提供了数字比例积分环路滤波器。 第一比例放大单元将相位误差值乘以第一比例环路增益，并且第一积分放大单元将相位误差累积值乘以第一积分环路增益。 第二比例放大单元将相位误差值乘以第二比例环路增益，第二积分放大单元将相位误差累积值乘以第二积分环路增益。 第一偏移值生成单元通过从第一比例环增益中减去第二比例环增益并将结果值乘以相位误差平均值来生成第一偏移值，第二偏移值生成单元通过减去第二偏移值生成单位生成第二偏移值 来自第一积分环路增益的第二积分环路增益，并将得到的值乘以相位误差累积平均值。

公开(公告)号：US20110150138A1

公开(公告)日：2011-06-23

申请号：US12970899

申请日：2010-12-16

申请人： Jung Woo PARK ,  Young Jae Lee ,  Hyun Kyu Yu ,  Byung Hun Min ,  Seong Do Kim ,  Hoai Nam Nguyen ,  Sang Gug Lee

发明人： Jung Woo PARK ,  Young Jae Lee ,  Hyun Kyu Yu ,  Byung Hun Min ,  Seong Do Kim ,  Hoai Nam Nguyen ,  Sang Gug Lee

IPC分类号： H03K9/00

CPC分类号： H04L25/08 ,  H03D7/1441 ,  H03D7/1458 ,  H03H19/004

摘要： A direct conversion receiver includes: a high linearity mixer device including a sampler unit charge-sampling an input current according to a sampling frequency, and a buffer unit receiving an output signal from the sampler unit while having a low input impedance, amplifying the received signal, and outputting a current signal; and a filter device decimating an output signal from the mixer device and FIR-filtering the decimated signal.

摘要翻译： 直接转换接收机包括：高线性混频器装置，包括：采样单元，根据采样频率对输入电流进行采样;以及缓冲单元，其具有低输入阻抗，从采样器单元接收输出信号，放大接收信号 ，并输出电流信号; 以及滤波器装置对来自混频器装置的输出信号进行抽取，并对抽取的信号进行FIR滤波。

公开(公告)号：US08193842B2

公开(公告)日：2012-06-05

申请号：US13344513

申请日：2012-01-05

申请人： Byung Hun Min ,  Hyun Kyu Yu

发明人： Byung Hun Min ,  Hyun Kyu Yu

IPC分类号： H03L7/06

CPC分类号： H03L7/091 ,  H03L7/085 ,  H03L7/107 ,  H03L7/1075 ,  H03L7/183 ,  H03L2207/06 ,  H03L2207/50

摘要： There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output frequency of the frequency oscillator at a variable division ratio; a counter unit receiving an output signal of the programmable divider and a reference frequency to generate a count value by counting rising edges of the output signal of the programmable divider during one cycle of the reference frequency, and outputting a first hit signal when the count value is 1, and outputting a second hit signal when the count value is 2; and a phase detection unit outputting a control bit obtained by subtracting a fractional error of the output signal of the programmable divider from a fractional error at a locked phase obtained from the count value and the reference frequency.

公开(公告)号：US08115525B2

公开(公告)日：2012-02-14

申请号：US12626554

申请日：2009-11-25

申请人： Byung Hun Min ,  Hyun Kyu Yu

发明人： Byung Hun Min ,  Hyun Kyu Yu

IPC分类号： H03L7/06

CPC分类号： H03L7/091 ,  H03L7/085 ,  H03L7/107 ,  H03L7/1075 ,  H03L7/183 ,  H03L2207/06 ,  H03L2207/50

摘要： There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output frequency of the frequency oscillator at a variable division ratio; a counter unit receiving an output signal of the programmable divider and a reference frequency to generate a count value by counting rising edges of the output signal of the programmable divider during one cycle of the reference frequency, and outputting a first hit signal when the count value is 1, and outputting a second hit signal when the count value is 2; and a phase detection unit outputting a control bit obtained by subtracting a fractional error of the output signal of the programmable divider from a fractional error at a locked phase obtained from the count value and the reference frequency.

摘要翻译： 提供了一个频率合成器。 频率合成器包括根据控制位调节输出频率的频率振荡器; 具有预设的最小分频比的可编程分频器，所述编程分频器以可分分频比划分所述频率振荡器的输出频率; 接收可编程分频器的输出信号的计数器单元和参考频率，以在参考频率的一个周期期间对可编程分频器的输出信号的上升沿进行计数以产生计数值，并且当计数值 是1，并且当计数值为2时输出第二命中信号; 以及相位检测单元，输出通过从从计数值和参考频率获得的锁定相位的分数误差中减去可编程分频器的输出信号的分数误差而获得的控制位。

公开(公告)号：US08611466B2

公开(公告)日：2013-12-17

申请号：US13309873

申请日：2011-12-02

申请人： Young-Jae Lee ,  Byung Hun Min ,  Nguyen Hoai Nam

发明人： Young-Jae Lee ,  Byung Hun Min ,  Nguyen Hoai Nam

IPC分类号： H04L27/00

CPC分类号： H04L27/3809

摘要： Provided is a discrete time receiver having a structure capable of processing various broadband signals. The discrete time receiver uses a discrete time filter having a sampling frequency in a constant range so as to process a signal having an input frequency in a wide range and a wide bandwidth, so that it is possible to reduce current consumption and the area of the discrete time receiver. Since the discrete time receiver is easily integrated with a digital device, it is easy to design a chip using system on chip (SoC).

摘要翻译： 提供了具有能够处理各种宽带信号的结构的离散时间接收机。 离散时间接收机使用具有恒定范围的采样频率的离散时间滤波器，以处理具有宽范围和宽带宽的输入频率的信号，从而可以减少电流消耗和 离散时间接收机。 由于离散时间接收器易于与数字设备集成，所以使用片上系统（SoC）设计芯片很容易。