公开(公告)号：US20090134944A1

公开(公告)日：2009-05-28

申请号：US12114705

申请日：2008-05-02

申请人： Ja Yol Lee ,  Sang Heung Lee ,  Hae Cheon Kim ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Sang Heung Lee ,  Hae Cheon Kim ,  Hyun Kyu Yu

IPC分类号： H03B5/12

CPC分类号： H03B5/1231 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/1253

摘要： A capacitive-degeneration double cross-coupled voltage-controlled oscillator is provided. The capacitive-degeneration double cross-coupled voltage-controlled oscillator includes a main cross-coupled oscillating unit including an oscillation transistor pair cross-coupled to first and second output nodes of a resonating unit to perform an oscillation operation; and an auxiliary cross-coupled oscillating unit including a positive-feedback transistor pair cross-coupled to the first and second output nodes and the transistor pair of the main cross-coupled oscillating unit and a degeneration capacitance connected between emitters of the positive-feedback transistor pair so as to increase a negative resistance of the main cross-coupled oscillating unit. Accordingly, it is possible to increase a maximum attainable oscillation frequency and to decrease an input capacitance.

摘要翻译： 提供电容变性双交叉耦合压控振荡器。 电容变性双交叉电压控制振荡器包括主交叉耦合振荡单元，其包括交叉耦合到谐振单元的第一和第二输出节点的振荡晶体管对，以执行振荡操作; 以及辅助交叉耦合振荡单元，其包括交叉耦合到第一和第二输出节点的正反馈晶体管对和主交叉耦合振荡单元的晶体管对，以及连接在正反馈晶体管的发射极之间的退化电容 以增加主交叉振荡单元的负电阻。 因此，可以增加最大可获得的振荡频率并降低输入电容。

公开(公告)号：US07902930B2

公开(公告)日：2011-03-08

申请号：US11927957

申请日：2007-10-30

申请人： Ja Yol Lee ,  Sang Heung Lee ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Sang Heung Lee ,  Hyun Kyu Yu

IPC分类号： H03K3/03

CPC分类号： H03B5/1218 ,  H03B5/1231 ,  H03B2200/0074 ,  H03B2200/0078

摘要： Provided is a colpitts quadrature voltage controlled oscillator capable of obtaining quadrature orthogonal signals using a quadrature combination between a base and a collector of each transistor, without using an additional circuit such as a coupled transistor, a coupled transformer, a multiphase RC filter, etc. Accordingly, since nonlinearity, increased phase noise, a decrease in the Q-factor of an LC resonator, and increased power consumption can be avoided, a colpitts quadrature voltage controlled oscillator that has low phase noise, low electric power consumption, and a compact size can be implemented.

摘要翻译： 提供了一种能够在不使用诸如耦合晶体管，耦合变压器，多相RC滤波器等附加电路的情况下使用每个晶体管的基极和集电极之间的正交组合获得正交正交信号的绞合正交压控振荡器。 因此，由于可以避免非线性，增加的相位噪声，LC谐振器的Q因子的降低和功率消耗的增加，所以抑制相位噪声低，功耗低，尺寸紧凑的正交压控振荡器 可以实现。

公开(公告)号：US20080129392A1

公开(公告)日：2008-06-05

申请号：US11927957

申请日：2007-10-30

申请人： Ja Yol Lee ,  Sang Heung Lee ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Sang Heung Lee ,  Hyun Kyu Yu

IPC分类号： H03B27/00 ,  H03B5/12

CPC分类号： H03B5/1218 ,  H03B5/1231 ,  H03B2200/0074 ,  H03B2200/0078

摘要： Provided is a colpitts quadrature voltage controlled oscillator capable of obtaining quadrature orthogonal signals using a quadrature combination between a base and a collector of each transistor, without using an additional circuit such as a coupled transistor, a coupled transformer, a multiphase RC filter, etc. Accordingly, since nonlinearity, increased phase noise, a decrease in the Q-factor of an LC resonator, and increased power consumption can be avoided, a colpitts quadrature voltage controlled oscillator that has low phase noise, low electric power consumption, and a compact size can be implemented.

摘要翻译： 提供了一种能够在不使用诸如耦合晶体管，耦合变压器，多相RC滤波器等附加电路的情况下使用每个晶体管的基极和集电极之间的正交组合获得正交正交信号的绞合正交压控振荡器。 因此，由于可以避免非线性，增加的相位噪声，LC谐振器的Q因子的降低和功率消耗的增加，所以抑制相位噪声低，功耗低，尺寸紧凑的正交压控振荡器 可以实现。

公开(公告)号：US07852165B2

公开(公告)日：2010-12-14

申请号：US12114705

申请日：2008-05-02

申请人： Ja Yol Lee ,  Sang Heung Lee ,  Hae Cheon Kim ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Sang Heung Lee ,  Hae Cheon Kim ,  Hyun Kyu Yu

IPC分类号： H03B5/12

CPC分类号： H03B5/1231 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/1253

摘要： A capacitive-degeneration double cross-coupled voltage-controlled oscillator is provided. The capacitive-degeneration double cross-coupled voltage-controlled oscillator includes a main cross-coupled oscillating unit including an oscillation transistor pair cross-coupled to first and second output nodes of a resonating unit to perform an oscillation operation; and an auxiliary cross-coupled oscillating unit including a positive-feedback transistor pair cross-coupled to the first and second output nodes and the transistor pair of the main cross-coupled oscillating unit and a degeneration capacitance connected between emitters of the positive-feedback transistor pair so as to increase a negative resistance of the main cross-coupled oscillating unit. Accordingly, it is possible to increase a maximum attainable oscillation frequency and to decrease an input capacitance.

摘要翻译： 提供电容变性双交叉耦合压控振荡器。 电容变性双交叉电压控制振荡器包括主交叉耦合振荡单元，其包括交叉耦合到谐振单元的第一和第二输出节点的振荡晶体管对，以执行振荡操作; 以及辅助交叉耦合振荡单元，其包括交叉耦合到第一和第二输出节点的正反馈晶体管对和主交叉耦合振荡单元的晶体管对，以及连接在正反馈晶体管的发射极之间的退化电容 以增加主交叉振荡单元的负电阻。 因此，可以增加最大可获得的振荡频率并降低输入电容。

公开(公告)号：US07999707B2

公开(公告)日：2011-08-16

申请号：US12629020

申请日：2009-12-01

申请人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

发明人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

IPC分类号： H03M1/06

CPC分类号： G04F10/06 ,  H03L7/085 ,  H03L2207/50

摘要： An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N−1)th fragmented delay phases; an adding unit adding each of the first to the (N−1)th fragmented delay phases to the phase error to generate first to (N−1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N−1)th phase errors.

摘要翻译： 公开了用于补偿时间 - 数字转换器（TDC）的误差的装置，以从包括TDC的相位检测器和包括TDC误差的相位误差接收延迟相位并补偿TDC误差以具有时间 分辨率提高N倍（N是自然数）。 该装置包括：分段和乘法单元，将延迟相位分片N次（N是自然数），以产生第一至第（N-1）个分段延迟相位; 加法单元将第一到第（N-1）个分段延迟相位中的每一个相加到相位误差，以产生第一到第（N-1）个相位误差; 以及比较单元从相位误差和第一到第（N-1）个相位误差获取最接近实际相位误差的相位误差补偿值。

公开(公告)号：US20100134335A1

公开(公告)日：2010-06-03

申请号：US12629020

申请日：2009-12-01

申请人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

发明人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

IPC分类号： H03M1/06

CPC分类号： G04F10/06 ,  H03L7/085 ,  H03L2207/50

摘要： An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N−1)th fragmented delay phases; an adding unit adding each of the first to the (N−1)th fragmented delay phases to the phase error to generate first to (N−1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N−1)th phase errors.

摘要翻译： 公开了用于补偿时间 - 数字转换器（TDC）的误差的装置，以从包括TDC的相位检测器和包括TDC误差的相位误差接收延迟相位并补偿TDC误差以具有时间 分辨率提高N倍（N是自然数）。 该装置包括：分段和乘法单元，将延迟相位分片N次（N是自然数），以产生第一到第（N-1）个分段延迟相位; 加法单元将第一到第（N-1）个分段延迟相位中的每一个相加到相位误差，以产生第一到第（N-1）个相位误差; 以及比较单元从相位误差和第一到第（N-1）个相位误差获取最接近实际相位误差的相位误差补偿值。

公开(公告)号：US07511581B2

公开(公告)日：2009-03-31

申请号：US11634004

申请日：2006-12-05

申请人： Ja Yol Lee ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim ,  Sang Heung Lee

发明人： Ja Yol Lee ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim ,  Sang Heung Lee

IPC分类号： H03L7/00

CPC分类号： H03K23/667 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099 ,  H03L7/193

摘要： A wide-band multimode frequency synthesizer using a Phase Locked Loop (PLL) is provided. The multiband frequency synthesizer includes a multimode prescaler, a phase detector/a charge pump, a swallow type frequency divider, and a switching bank LC tuning voltage-controlled oscillator having wide-band and low phase noise characteristics. The multimode prescaler operates in five modes and divides a signal up to 12 GHz. The wide-band frequency synthesizer can be used in various fields such as WLAN/HYPERLAN/DSRC/UWB systems that operate in the frequency range from 2 GHz to 9 GHz. The wide-band multimode frequency synthesizer includes a frequency/phase detector for comparing a frequency and phase of a reference high-frequency signal with a frequency and phase of a feedback high-frequency signal; a charge pump for producing an output current corresponding to the result of the comparison performed by the frequency/phase detector; a loop filter for producing an output voltage corresponding to an accumulated value of the output current of the charge pump; a voltage-controlled oscillator for generating an oscillation signal having a frequency corresponding to the output voltage of the loop filter; and a variable frequency divider for dividing an output signal of the voltage-controlled oscillator by a designated integer value, and outputting the result as a feedback signal, wherein at lease two of an amount of unit pumping charges of the charge pump, an RLC value of the loop filter, an RLC value of the voltage-controlled oscillator, and a divisor value of the variable frequency divider are controlled according to a band.

摘要翻译： 提供了使用锁相环（PLL）的宽带多模频率合成器。 多频率频率合成器包括多模预分频器，相位检测器/电荷泵，燕子式分频器和具有宽带和低相位噪声特性的开关组LC调谐压控振荡器。 多模预分频器以五种模式工作，并将信号分为12 GHz。 宽带频率合成器可用于各种领域，例如在2 GHz至9 GHz频率范围内工作的WLAN / HYPERLAN / DSRC / UWB系统。 宽带多模频率合成器包括用于将参考高频信号的频率和相位与反馈高频信号的频率和相位进行比较的频率/相位检测器; 用于产生与由频率/相位检测器执行的比较结果相对应的输出电流的电荷泵; 环路滤波器，用于产生与电荷泵的输出电流的累积值相对应的输出电压; 用于产生具有与环路滤波器的输出电压对应的频率的振荡信号的压控振荡器; 以及可变分频器，用于将压控振荡器的输出信号除以指定的整数值，并输出该结果作为反馈信号，其中至少两个电荷泵的单位泵送电荷，RLC值 根据频带控制环路滤波器的电压控制振荡器的RLC值和可变分频器的除数值。

公开(公告)号：US20110148490A1

公开(公告)日：2011-06-23

申请号：US12956498

申请日：2010-11-30

申请人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

IPC分类号： H03L7/08 ,  H03M1/50

CPC分类号： H03L7/095 ,  G04F10/005 ,  H03L7/085 ,  H03L7/103 ,  H03L2207/50

摘要： An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.

摘要翻译： 全数字锁相环（ADPLL）包括：相位计数器累积频率设定字值和数字控制振荡器（DCO）时钟的相位，并检测参考时钟和重新定时钟之间的精细相位差; 相位检测器，根据所述精细相位差检测补偿所述频率设定字值与所述DCO时钟之间的相位差的数字相位误差值，以检测数字相位误差值; 数字环路滤波器滤除数字相位误差值并控制PLL的操作特性; 锁定检测器，根据数字环路滤波器的输出产生锁定指示信号; 数字控制振荡器根据数字环路滤波器的输出来改变DCO时钟的频率; 以及重新计时的时钟发生器，通过以低频再定时DCO时钟产生重定时钟。

公开(公告)号：US20100134192A1

公开(公告)日：2010-06-03

申请号：US12581105

申请日：2009-10-16

申请人： Byung Hun MIN ,  Ja Yol Lee ,  Seong Do Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu

发明人： Byung Hun MIN ,  Ja Yol Lee ,  Seong Do Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu

IPC分类号： H03L7/00

CPC分类号： H03L7/181 ,  H03L2207/50 ,  Y10S331/02

摘要： A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting a oscillation frequency according to control value; a programmable divider dividing the oscillation frequency according to a division ratio; a counter counting the number of clocks of the divided frequency by using a reference frequency; and a frequency detector outputting a value obtained by subtracting the number of the counted clocks from a reference comparison value, a value obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider, as the control value of the oscillator.

摘要翻译： 一种频率校准环路电路，具有预定的频道字（FCW）指令值，为了获得振荡器中的目标频率输入的比特和可编程分频器的预设最小分频比n（n是常数） 包括：振荡器根据控制值调节振荡频率; 一个可编程除法器根据分频比划分振荡频率; 通过使用参考频率对分频频率的时钟数进行计数的计数器; 输出通过从参考比较值中减去计数时钟数而得到的值的频率检测器，通过将频率通道字（FCW）指令值除以可编程分压器的最小分频比而获得的值作为控制值 的振荡器。

公开(公告)号：US07554416B2

公开(公告)日：2009-06-30

申请号：US11542288

申请日：2006-10-02

申请人： Ja Yol Lee ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim ,  Sang Heung Lee ,  Kyoung Ik Cho

发明人： Ja Yol Lee ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim ,  Sang Heung Lee ,  Kyoung Ik Cho

IPC分类号： H03B7/06 ,  H03C3/22 ,  H03L1/00

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1265 ,  H03B5/1271 ,  H03B2201/0208 ,  H03B2201/0266 ,  H03J2200/10

摘要： Provided is an LC resonance voltage-controlled oscillator (VCO) used for a multi-band multi-mode wireless transceiver. In order to generate a multi-band frequency, a capacitor bank and a switchable inductor are included in the LC resonance voltage-controlled oscillator. The LC resonance voltage-controlled oscillator employs an adjustable emitter-degeneration negative resistance cell in place of tail current sources in order to compensate for non-uniform oscillation amplitude caused by the capacitor bank and prevent the degradation of a phase noise due to the tail current sources. The LC resonance voltage-controlled oscillator includes an inductor providing an inductance element partially determining the frequency of an oscillation wave; a discrete capacitor bank providing a capacitance element partially determining the frequency of the oscillation wave and being discretely determined by a control bit signal; and a discrete negative resistance cell providing a negative resistance element that is discretely determined by the control bit signal, to keep the amplitude of the oscillation wave constant.

摘要翻译： 提供了一种用于多频带多模无线收发器的LC谐振压控振荡器（VCO）。 为了产生多频带频率，LC谐振压控振荡器中包括电容器组和可切换电感器。 LC谐振压控振荡器代替尾电流源采用可调发射极 - 退化负电阻电池，以补偿由电容器组引起的不均匀振荡幅度，并防止由于尾电流导致的相位噪声的降低 来源。 LC谐振电压控制振荡器包括：电感器，其提供部分地确定振荡波频率的电感元件; 分立电容器组，提供部分地确定振荡波的频率并由控制位信号离散地确定的电容元件; 以及提供由控制位信号离散地确定的负电阻元件的离散负电阻单元，以保持振荡波的幅度恒定。