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    Body capacitor for SOI memory description
    1.
    发明授权
    Body capacitor for SOI memory description 有权
    用于SOI存储器描述的体电容

    公开(公告)号：US07232745B2

    公开(公告)日：2007-06-19

    申请号：US11064730

    申请日：2005-02-24

    申请人： Jack A. Mandelman ,  Louis C. Hsu ,  Rajiv Vasant Joshi

    发明人： Jack A. Mandelman ,  Louis C. Hsu ,  Rajiv Vasant Joshi

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/84 ,  H01L27/108 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/1203 ,  H01L29/94

    摘要： A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between the SL and the bitline diffusions and the body capacitance plate is precisely controlled. More specifically, the present invention forms the structure of a 1T-capacitorless SOI body charge storage cell having sidewall capacitor plates using a process that assures that there is 1) minimal overlap between plate and source/drain diffusions, and 2) that the minimal overlap obtained in the present invention is precisely controlled and is not subject to alignment tolerances. The inventive cell results in larger signal margin, improved performance, smaller chip size, and reduced dynamic power dissipation relative to the prior art.

    摘要翻译： 提供一种具有体电容板的半导体结构，其形成有确保体电容板与源极线（SL）扩散和位线扩散两者自对准的工艺。 因此，SL和位线扩散和体电容板之间的重叠量被精确地控制。 更具体地说，本发明通过使用确保存在1）板和源极/漏极扩散之间的最小重叠的过程形成具有侧壁电容器板的1T无电容的SOI体电荷存储单元的结构，以及2）最小重叠 在本发明中获得的精确控制并且不受对准公差的影响。 与现有技术相比，本发明的电池产生更大的信号余量，改善的性能，更小的芯片尺寸和降低的动态功耗。

    SOI field effect transistor with a back gate for modulating a floating body
    2.
    发明授权
    SOI field effect transistor with a back gate for modulating a floating body 失效
    具有用于调制浮体的背栅的SOI场效应晶体管

    公开(公告)号：US07772649B2

    公开(公告)日：2010-08-10

    申请号：US12036325

    申请日：2008-02-25

    申请人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  Carl Radens ,  William Tonti

    发明人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  Carl Radens ,  William Tonti

    IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

    CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78648

    摘要： A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulator layer within the area of the opening to form damaged buried insulator region. The shallow trench isolation structure is removed and the damaged buried insulator region is etched selective to undamaged buried insulator portions to form a cavity. A dielectric layer is formed on the sidewalls and the exposed bottom surface of the top semiconductor region and a back gate filling the cavity is formed. A contact is formed to provide an electrical bias to the back gate so that the electrical potential of the body and the first source/drain region is electrically modulated.

    摘要翻译： 将掩模层施加在顶部半导体层上并且被图案化以在开口中暴露浅沟槽隔离结构以及要在其中形成第一源极/漏极区域和主体的顶部半导体区域的一部分。 将离子注入到开口区域内的埋入绝缘体层的一部分中以形成损坏的埋层绝缘体区域。 去除浅沟槽隔离结构，并且损坏的埋层绝缘体区域被选择性地蚀刻到未损坏的埋入绝缘体部分以形成空腔。 在顶部半导体区域的侧壁和暴露的底表面上形成介电层，并且形成填充空腔的背栅。 形成接触以向后栅极提供电偏压，使得主体和第一源极/漏极区域的电势被电调制。

    SOI CMOS COMPATIBLE MULTIPLANAR CAPACITOR
    3.
    发明申请
    SOI CMOS COMPATIBLE MULTIPLANAR CAPACITOR 有权
    SOI CMOS兼容多元电容器

    公开(公告)号：US20090072290A1

    公开(公告)日：2009-03-19

    申请号：US11857770

    申请日：2007-09-19

    申请人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  William Tonti

    发明人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  William Tonti

    IPC分类号： H01L21/70 ,  H01L27/108

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10861 ,  H01L28/60

    摘要： An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode.

    摘要翻译： 孤立的浅沟槽隔离部分形成在绝缘体上半导体衬底的顶部半导体部分以及浅沟槽隔离结构中。 环形形状的沟槽形成在掺杂顶部半导体部分周围，并填充有诸如掺杂多晶硅的导电材料。 隔离的浅沟槽隔离部分和由导电材料的环限定的掩​​埋绝缘体层的部分被蚀刻以形成空腔。 在空腔内的暴露的半导体表面上和掺杂的顶部半导体部分之上形成电容器电介质。 形成在沟槽中并且在掺杂顶部半导体部分上方的导电材料部分构成电容器的内部电极，而导电材料的环，掺杂的顶部半导体部分和与电容器电介质邻接的手柄衬底的一部分构成一个 第二电极。

    Method of fabricating a body capacitor for SOI memory
    7.
    发明授权
    Method of fabricating a body capacitor for SOI memory 有权
    制造用于SOI存储器的体电容器的方法

    公开(公告)号：US07390730B2

    公开(公告)日：2008-06-24

    申请号：US11742147

    申请日：2007-04-30

    申请人： Jack A. Mandelman ,  Louis C. Hsu ,  Rajiv V. Joshi

    发明人： Jack A. Mandelman ,  Louis C. Hsu ,  Rajiv V. Joshi

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/84 ,  H01L27/108 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/1203 ,  H01L29/94

    摘要： A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between the SL and the bitline diffusions and the body capacitance plate is precisely controlled. More specifically, the present invention forms the structure of a 1T-capacitorless SOI body charge storage cell having sidewall capacitor plates using a process that assures that there is 1) minimal overlap between plate and source/drain diffusions, and 2) that the minimal overlap obtained in the present invention is precisely controlled and is not subject to alignment tolerances. The inventive cell results in larger signal margin, improved performance, smaller chip size, and reduced dynamic power dissipation relative to the prior art.

    摘要翻译： 提供一种具有体电容板的半导体结构，其形成有确保体电容板与源极线（SL）扩散和位线扩散两者自对准的工艺。 因此，SL和位线扩散和体电容板之间的重叠量被精确地控制。 更具体地说，本发明通过使用确保存在1）板和源极/漏极扩散之间的最小重叠的过程形成具有侧壁电容器板的1T无电容的SOI体电荷存储单元的结构，以及2）最小重叠 在本发明中获得的精确控制并且不受对准公差的影响。 与现有技术相比，本发明的电池产生更大的信号余量，改善的性能，更小的芯片尺寸和降低的动态功耗。

    SOI FIELD EFFECT TRANSISTOR WITH A BACK GATE FOR MODULATING A FLOATING BODY
    8.
    发明申请
    SOI FIELD EFFECT TRANSISTOR WITH A BACK GATE FOR MODULATING A FLOATING BODY 失效
    具有用于调制浮动体的后盖的SOI场效应晶体管

    公开(公告)号：US20090212362A1

    公开(公告)日：2009-08-27

    申请号：US12036325

    申请日：2008-02-25

    申请人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  Carl Radens ,  William Tonti

    发明人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  Carl Radens ,  William Tonti

    IPC分类号： H01L21/84 ,  H01L29/786

    CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78648

    摘要： A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulator layer within the area of the opening to form damaged buried insulator region. The shallow trench isolation structure is removed and the damaged buried insulator region is etched selective to undamaged buried insulator portions to form a cavity. A dielectric layer is formed on the sidewalls and the exposed bottom surface of the top semiconductor region and a back gate filling the cavity is formed. A contact is formed to provide an electrical bias to the back gate so that the electrical potential of the body and the first source/drain region is electrically modulated.

    摘要翻译： 将掩模层施加在顶部半导体层上并且被图案化以在开口中暴露浅沟槽隔离结构以及要在其中形成第一源极/漏极区域和主体的顶部半导体区域的一部分。 将离子注入到开口区域内的埋入绝缘体层的一部分中以形成损坏的埋层绝缘体区域。 去除浅沟槽隔离结构，并且损坏的埋层绝缘体区域被选择性地蚀刻到未损坏的埋入绝缘体部分以形成空腔。 在顶部半导体区域的侧壁和暴露的底表面上形成介电层，并且形成填充空腔的背栅。 形成接触以向后栅极提供电偏压，使得主体和第一源极/漏极区域的电势被电调制。

    METHOD AND APPARATUS FOR WAFER EDGE CLEANING
    10.
    发明申请
    METHOD AND APPARATUS FOR WAFER EDGE CLEANING 审中-公开
    WAFER EDGE清洗方法和装置

    公开(公告)号：US20080289651A1

    公开(公告)日：2008-11-27

    申请号：US11753711

    申请日：2007-05-25

    申请人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman

    发明人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman

    IPC分类号： B08B6/00

    CPC分类号： B08B7/0042 ,  H01L21/02087 ,  H01L21/67069 ,  H01L21/67086

    摘要： A wafer edge cleaning system that includes a wafer dry etching chamber and one or more irradiation sources preferably positioned inside the wafer dry etching chamber. The irradiation source such as laser generates a beam aimed at the periphery of the wafer to melt any defects, in particular, black silicon at the edge of the wafer. Preferably, the wafer is mounted on a rotating platform. The invention further provides a method for removing black silicon at the edge of a semiconductor wafer that includes the steps of: patterning the wafer with a trench mask layer; etching the wafer to form a trench thereon; exposing the edge of the wafer to a laser beam to melt the black silicon thereon; stripping the mask and cleaning the wafer.

    摘要翻译： 一种晶片边缘清洁系统，其包括晶片干蚀刻室和优选位于晶片干蚀刻室内部的一个或多个照射源。 诸如激光器的照射源产生瞄准晶片周边的光束，以熔化晶片边缘的任何缺陷，特别是黑色硅。 优选地，晶片安装在旋转平台上。 本发明还提供一种在半导体晶片的边缘处去除黑硅的方法，包括以下步骤：用沟槽掩模层图案化晶片; 蚀刻晶片以在其上形成沟槽; 将晶片的边缘暴露于激光束以在其上熔化黑色硅; 剥去掩模并清洁晶片。