公开(公告)号：US06479368B1

公开(公告)日：2002-11-12

申请号：US09033067

申请日：1998-03-02

申请人： Jack A. Mandelman ,  Mutsuo Morikado ,  Herbert Ho ,  Jeffrey P. Gambino

发明人： Jack A. Mandelman ,  Mutsuo Morikado ,  Herbert Ho ,  Jeffrey P. Gambino

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A method of manufacturing a semiconductor device, in which the depth of a divot in a shallow trench isolation can be decreased. The method comprises forming a trench in a semiconductor substrate, for isolating elements, forming a nitride film on a surface of the trench, depositing mask material on an entire surface of the semiconductor substrate, filling the trench with the mask material, etching the mask material until a surface level of the mask material in the trench falls below the surface of the semiconductor substrate, removing an exposed upper portion of the nitride film on the surface of the trench, removing the mask material from the trench, filling the trench with element-isolating material, thereby forming an element-isolating region, and forming a transistor in an element region isolated from another element region by the element-isolating region.

摘要翻译： 一种制造半导体器件的方法，其中可以减少浅沟槽隔离中的凹陷的深度。 该方法包括在半导体衬底中形成沟槽，用于隔离元件，在沟槽的表面上形成氮化物膜，在半导体衬底的整个表面上沉积掩模材料，用掩模材料填充沟槽，蚀刻掩模材料 直到沟槽中的掩模材料的表面水平落在半导体衬底的表面之下，去除沟槽表面上暴露的氮化物膜的上部，从沟槽中去除掩模材料， 从而形成元件隔离区域，并且通过元件隔离区域在与另一个元件区域隔离的元件区域中形成晶体管。

公开(公告)号：US07750404B2

公开(公告)日：2010-07-06

申请号：US11843337

申请日：2007-08-22

申请人： Mutsuo Morikado

发明人： Mutsuo Morikado

IPC分类号： H01L27/01

CPC分类号： H01L29/78648 ,  H01L29/78654

摘要： According to an aspect of the present invention, there is provided a semiconductor device including an insulated gate field effect transistor including a gate electrode film formed, via a gate insulating film, on a semiconductor film formed on a support substrate via an insulating film, and a source region and drain region formed in the semiconductor film to sandwich the gate electrode film in a gate length direction, a support substrate contact including a polysilicon film formed on a first opening via a silicon oxide film, the first opening extending through the semiconductor film and the insulating film and reaching the support substrate, an interlayer dielectric film formed on the semiconductor film and the support substrate contact, and an interconnection connected to the polysilicon film via a conductive material, the conductive material filling a second opening, which extends through the interlayer dielectric film and reaches the support substrate contact.

摘要翻译： 根据本发明的一个方面，提供了一种半导体器件，其包括绝缘栅场效应晶体管，其包括通过栅极绝缘膜在经由绝缘膜形成在支撑基板上的半导体膜上形成的栅极电极膜，以及 源极区和漏极区，形成在半导体膜中以沿栅极长度方向夹持栅极电极膜;支撑衬底接触，包括通过氧化硅膜形成在第一开口上的多晶硅膜，第一开口延伸穿过半导体膜 绝缘膜到达支撑基板，形成在半导体膜和支撑基板上的层间绝缘膜接触，以及通过导电材料与多晶硅膜连接的布线，所述导电材料填充第二开口，该第二开口延伸穿过 层间绝缘膜并到达支撑基板接触。

公开(公告)号：US20090206390A1

公开(公告)日：2009-08-20

申请号：US12337265

申请日：2008-12-17

申请人： Mutsuo Morikado

发明人： Mutsuo Morikado

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

摘要： A nonvolatile semiconductor device and method having a plurality of series-connected memory cells with floating and control gate electrodes, and a first insulating layer formed between the gate electrodes. One of the memory cells has the floating gate formed to contact the control gate electrode through an aperture in the insulating layer. The insulating layer is removed to form spaces between the gate electrodes. A second insulating film is formed in the spaces between the gate electrodes. The dummy electrode supports the series of gate electrodes to maintain the spaces between the electrodes. The second insulating layer is formed to be continuous in the spaces and on side surfaces of the gate electrodes. The second insulating layer may have a stacked structure with n layers in the spaces and (n−1)/2 layers on the side surfaces.

摘要翻译： 一种非易失性半导体器件和方法，具有多个具有浮置和控制栅电极的串联存储单元，以及形成在栅电极之间的第一绝缘层。 一个存储单元具有形成为通过绝缘层中的孔与控制栅电极接触的浮动栅极。 去除绝缘层以在栅电极之间形成空间。 在栅电极之间的空间中形成第二绝缘膜。 虚拟电极支持一系列栅电极以保持电极之间的空间。 第二绝缘层形成为在栅电极的空间和侧表面中是连续的。 第二绝缘层可以具有在空间中具有n层的层叠结构，并且在侧表面上具有（n-1）/ 2层。

公开(公告)号：US07433234B2

公开(公告)日：2008-10-07

申请号：US11296311

申请日：2005-12-08

申请人： Mutsuo Morikado

发明人： Mutsuo Morikado

IPC分类号： G11C11/404 ,  H01L27/01

CPC分类号： H01L29/7841 ,  G11C11/4074 ,  G11C2211/4016 ,  H01L27/10802

摘要： A semiconductor storage device including a memory cell. In the memory cell a buried electrode is formed on a semiconductor substrate. A semiconductor layer is formed on the buried electrode via a buried insulating film. A surface electrode is formed on the semiconductor layer via an insulating film. A source region and drain region are formed in the semiconductor layer on both sides of the surface electrode with a predetermined spacing therebetween. A floating body is formed between the source region and drain region, which stores data in accordance with whether holes are stored in the floating body. The buried electrode serves as a gate electrode, and the surface electrode serves as a plate electrode.

摘要翻译： 一种包括存储单元的半导体存储装置。 在存储单元中，在半导体衬底上形成掩埋电极。 通过掩埋绝缘膜在掩埋电极上形成半导体层。 表面电极通过绝缘膜形成在半导体层上。 源极区域和漏极区域以规定间隔形成在表面电极两侧的半导体层中。 在源极区域和漏极区域之间形成浮体，其根据孔是否存储在浮体中而存储数据。 埋电极用作栅电极，表面电极用作平板电极。

公开(公告)号：US20060244106A1

公开(公告)日：2006-11-02

申请号：US11478742

申请日：2006-06-30

申请人： Mutsuo Morikado

发明人： Mutsuo Morikado

IPC分类号： H01L29/40

CPC分类号： H01L27/10829 ,  H01L21/84 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10838 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78609

摘要： A semiconductor device includes second to fourth semiconductor layers, a gate electrode, and an insulating film. The second semiconductor layer is formed on a first semiconductor layer and has a projecting shape. The third and fourth semiconductor layers are formed on the first semiconductor layer to be in contact with the second semiconductor layer and oppose each other via the second semiconductor layer. The gate electrode is in contact with the second semiconductor layer with a gate insulating film interposed therebetween and forms a channel in the second semiconductor layer. The insulating film is formed in the first semiconductor layer located immediately under the third and fourth semiconductor layers.

摘要翻译： 半导体器件包括第二至第四半导体层，栅电极和绝缘膜。 第二半导体层形成在第一半导体层上并具有突出形状。 第三和第四半导体层形成在第一半导体层上以与第二半导体层接触并且经由第二半导体层彼此相对。 栅电极与第二半导体层接触，栅极绝缘膜插入其间，并在第二半导体层中形成沟道。 绝缘膜形成在位于第三和第四半导体层正下方的第一半导体层中。

公开(公告)号：US08369152B2

公开(公告)日：2013-02-05

申请号：US12817665

申请日：2010-06-17

申请人： Takeshi Shimane ,  Naoyuki Shigyo ,  Mutsuo Morikado

发明人： Takeshi Shimane ,  Naoyuki Shigyo ,  Mutsuo Morikado

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： H01L27/11568 ,  G11C16/0483 ,  G11C16/10

摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cells without a source region and a drain region, and a first insulating film. The memory cells are arranged adjacent to one another on the semiconductor substrate and include a first gate electrode including a charge accumulation layer. A current path functioning as a source region or a drain region of a selected memory cell is formed in the semiconductor substrate when a voltage is applied to the first gate electrode of one of unselected memory cells. The first insulating film is formed on the semiconductor substrate to fill a region between the first gate electrodes of the memory cells adjacent to each other.

摘要翻译： 根据一个实施例，半导体存储器件包括半导体衬底，没有源极区和漏极区的存储单元和第一绝缘膜。 存储单元在半导体衬底上彼此相邻地布置，并且包括包括电荷累积层的第一栅电极。 当向未选择的存储单元之一的第一栅电极施加电压时，在半导体衬底中形成用作所选存储单元的源极区或漏极区的电流路径。 第一绝缘膜形成在半导体衬底上以填充彼此相邻的存储单元的第一栅电极之间的区域。

公开(公告)号：US08362543B2

公开(公告)日：2013-01-29

申请号：US12337265

申请日：2008-12-17

申请人： Mutsuo Morikado

发明人： Mutsuo Morikado

IPC分类号： H01L29/72

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

摘要： A nonvolatile semiconductor device and method having a plurality of series-connected memory cells with floating and control gate electrodes, and a first insulating layer formed between the gate electrodes. One of the memory cells has the floating gate formed to contact the control gate electrode through an aperture in the insulating layer. The insulating layer is removed to form spaces between the gate electrodes. A second insulating film is formed in the spaces between the gate electrodes. The dummy electrode supports the series of gate electrodes to maintain the spaces between the electrodes. The second insulating layer is formed to be continuous in the spaces and on side surfaces of the gate electrodes. The second insulating layer may have a stacked structure with n layers in the spaces and (n−1)/2 layers on the side surfaces.

摘要翻译： 一种非易失性半导体器件和方法，具有多个具有浮置和控制栅电极的串联存储单元，以及形成在栅电极之间的第一绝缘层。 一个存储单元具有形成为通过绝缘层中的孔与控制栅电极接触的浮动栅极。 去除绝缘层以在栅电极之间形成空间。 在栅电极之间的空间中形成第二绝缘膜。 虚拟电极支持一系列栅电极以保持电极之间的空间。 第二绝缘层形成为在栅电极的空间和侧表面中是连续的。 第二绝缘层可以具有在空间中具有n层的层叠结构，并且在侧表面上具有（n-1）/ 2层。

公开(公告)号：US08358537B2

公开(公告)日：2013-01-22

申请号：US13235410

申请日：2011-09-18

申请人： Mutsuo Morikado

发明人： Mutsuo Morikado

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3418

摘要： A nonvolatile semiconductor memory device according to one embodiment includes: a memory cell array; word lines each connected to nonvolatile memory cells; and a control circuit. When executing the data reading operation, the control circuit applies to a selected word line connected to a selected memory cell a first voltage obtained by adding a first adjusting voltage to an intermediate voltage between adjoining two of the threshold voltage distributions; applies to first non-selected word lines adjoining the selected word line a second voltage obtained by subtracting a second adjusting voltage from a reading pass voltage; applies to second non-selected word lines adjoining the first non-selected word lines a third voltage obtained by adding the second adjusting voltage to the reading pass voltage; and applies to third non-selected word lines, the third non-selected word lines being non-selected word lines except the first and second non-selected word lines, the reading pass voltage.

摘要翻译： 根据一个实施例的非易失性半导体存储器件包括：存储单元阵列; 每条字线连接到非易失性存储单元; 和控制电路。 当执行数据读取操作时，控制电路通过将相邻的两个阈值电压分布之间的中间电压加上第一调整电压而获得的第一电压施加到与所选存储单元连接的选定字线上; 通过从所述读取通过电压中减去第二调整电压而得到的第二电压施加与所述选定字线相邻的第一非选择字线; 适用于与第一非选择字线邻接的第二非选择字线，通过将第二调整电压加到读取通过电压而获得的第三电压; 并且适用于第三非选择字线，第三未选择字线是除第一和第二未选择字线以外的非选择字线，读取通过电压。

公开(公告)号：US20100155812A1

公开(公告)日：2010-06-24

申请号：US12642073

申请日：2009-12-18

申请人： Mutsuo Morikado ,  Kiyomi Naruke ,  Hiroaki Tsunoda ,  Tohru Maruyama ,  Fumitaka Arai

发明人： Mutsuo Morikado ,  Kiyomi Naruke ,  Hiroaki Tsunoda ,  Tohru Maruyama ,  Fumitaka Arai

IPC分类号： H01L27/115 ,  H01L21/336 ,  H01L21/8246 ,  H01L29/788

CPC分类号： H01L21/28273 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile memory of a semiconductor device has a tunnel insulation film provided on the active area; a floating gate electrode provided on the tunnel insulation film; a control gate electrode provided over the floating gate electrode; and an inter-electrode insulation film provided between the floating gate electrode and the control gate electrode, wherein, in a section of the non-volatile memory cell in a channel width direction, a dimension of a top face of the active area in the channel width direction is equal to or less than a dimension of a top face of the tunnel insulation film in the channel width direction, and the dimension of the top face of the tunnel insulation film in the channel width direction is less than a dimension of a bottom face of the floating gate electrode in the channel width direction.

摘要翻译： 半导体器件的非易失性存储器具有设置在有源区上的隧道绝缘膜; 设置在隧道绝缘膜上的浮栅电极; 设置在所述浮栅上的控制栅极; 以及设置在所述浮栅电极和所述控制栅电极之间的电极间绝缘膜，其中，在所述非易失性存储单元的沟道宽度方向的截面中，所述沟道中的有效区域的顶面的尺寸 宽度方向等于或小于通道宽度方向上的隧道绝缘膜的顶面的尺寸，并且隧道绝缘膜在沟道宽度方向上的尺寸小于底部的尺寸 在沟道宽度方向上的浮栅电极的表面。

公开(公告)号：US08349720B2

公开(公告)日：2013-01-08

申请号：US13415942

申请日：2012-03-09

申请人： Mutsuo Morikado

发明人： Mutsuo Morikado

IPC分类号： H01L21/283

CPC分类号： H01L29/42336 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory includes a memory cell string having a plurality of memory cell transistors connected in series, a selection gate transistor connected in series with one end of the memory cell string, and having a gate electrode provided on a gate insulating film on a semiconductor substrate, and an element isolation insulating layer which is provided in the semiconductor substrate. The gate electrode includes a first gate electrode provided on the gate insulating film, a first and second insulating films provided on the first gate electrode, and a second gate electrode provided on the second insulating film and the element isolation insulating layer, and electrically connected to the first gate electrode. An first upper surface portion of the element isolation insulating layer below the second gate electrode is leveled with an upper surface of the first gate electrode.

摘要翻译： 非易失性半导体存储器包括具有串联连接的多个存储单元晶体管的存储单元串，与存储单元串的一端串联连接的选择栅极晶体管，并且具有设置在半导体上的栅极绝缘膜上的栅电极 基板和设置在半导体基板中的元件隔离绝缘层。 栅电极包括设置在栅极绝缘膜上的第一栅电极，设置在第一栅电极上的第一绝缘膜和第二绝缘膜，以及设置在第二绝缘膜和元件隔离绝缘层上的第二栅电极， 第一栅电极。 第二栅电极下方的元件隔离绝缘层的第一上表面部分与第一栅电极的上表面平齐。