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    Bit line pre-charge circuit of semiconductor memory device
    1.
    发明授权
    Bit line pre-charge circuit of semiconductor memory device 有权
    半导体存储器件的位线预充电电路

    公开(公告)号：US06909654B2

    公开(公告)日：2005-06-21

    申请号：US10633562

    申请日：2003-08-05

    申请人： Jae-Hoon Joo ,  Jin-Seok Lee ,  Sang-Seok Kang ,  Kyu-Chan Lee ,  Byung-Heon Kwak ,  Byung-Chul Kim

    发明人： Jae-Hoon Joo ,  Jin-Seok Lee ,  Sang-Seok Kang ,  Kyu-Chan Lee ,  Byung-Heon Kwak ,  Byung-Chul Kim

    IPC分类号： H01L27/108 ,  G11C7/12 ,  G11C11/401 ,  G11C11/409 ,  H01L21/8242 ,  G11C7/00

    CPC分类号： G11C7/12 ,  G11C2207/2227

    摘要： A bit line pre-charge circuit of a semiconductor memory device includes a pre-charge circuit connected between a pair of bit lines for pre-charging the pair of bit lines in response to a pre-charge control signal and a pre-charge voltage transmitting circuit for transmitting a pre-charge voltage to the pre-charge circuit in response to the pre-charge control signal. A voltage drop in a pre-charge voltage generation line may be prevented when a short circuit is formed between a word line and a pair of bit lines, and current consumption during a standby operation of the semiconductor memory device may also be reduced, by preventing current from flowing from the pair of bit lines to the pre-charge voltage generation line.

    摘要翻译： 半导体存储器件的位线预充电电路包括连接在一对位线之间的预充电电路，用于响应于预充电控制信号和预充电电压发射来对该对位线进行预充电 电路，用于响应于预充电控制信号将预充电电压发送到预充电电路。 当在字线和一对位线之间形成短路时，可以防止预充电电压产生线中的电压降，并且还可以通过防止在半导体存储器件的待机操作期间的电流消耗 电流从一对位线流向预充电电压产生线。

    Semiconductor device
    2.
    发明申请
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号：US20060132183A1

    公开(公告)日：2006-06-22

    申请号：US11312953

    申请日：2005-12-19

    申请人： Dong-Jin Lim ,  Sang-Seok Kang ,  Byung-Heon Kwak ,  Jae-Hoon Joo ,  Chang-Hag Oh

    发明人： Dong-Jin Lim ,  Sang-Seok Kang ,  Byung-Heon Kwak ,  Jae-Hoon Joo ,  Chang-Hag Oh

    IPC分类号： H03K19/094

    CPC分类号： H03K19/00323

    摘要： A semiconductor device that performs stable circuit operations is provided. The device includes: a pull-up driver for pulling up a first node in response to first states of input and control signals; a pull-down driver for pulling down a second node in response to a second state of the input signal; at least one fuse connected between the first node and the second node; a latch for generating an output signal to maintain the state of the second node; and a controller for generating the control signal that is maintained in a first state when the input signal is in the second state, and maintained in the first state and then transitioned to the second state after a predetermined delay time when the input signal is transitioned to the first state. In this construction, even if the fuse is incompletely cut during a process of cutting the fuse, the pull-up driver or the pull-down driver is turned off, thus preventing unnecessary current flow in advance.

    摘要翻译： 提供了执行稳定电路操作的半导体器件。 所述装置包括：用于响应于输入和控制信号的第一状态而拉起第一节点的上拉驱动器; 用于响应于所述输入信号的第二状态来拉下第二节点的下拉驱动器; 连接在第一节点和第二节点之间的至少一个熔丝; 用于产生输出信号以保持第二节点的状态的锁存器; 以及控制器，用于当输入信号处于第二状态时产生保持在第一状态的控制信号，并且当输入信号转换到预定的延迟时间后，保持在第一状态，然后转变到第二状态 第一个状态。 在这种结构中，即使在切断保险丝的过程中保险丝不完全切断，则上拉驱动器或下拉驱动器被关闭，从而防止事先不必要的电流流动。

    Semiconductor memory device and test system of a semiconductor memory device
    3.
    发明申请
    Semiconductor memory device and test system of a semiconductor memory device 审中-公开
    一种半导体存储器件的半导体存储器件和测试系统

    公开(公告)号：US20090044063A1

    公开(公告)日：2009-02-12

    申请号：US11974342

    申请日：2007-10-12

    申请人： Yong-Hwan Cho ,  Byung-Heon Kwak ,  Hyun-Soon Jang ,  Jae-Hoon Joo ,  Seung-Whan Seo ,  Jong-Hyoung Lim

    发明人： Yong-Hwan Cho ,  Byung-Heon Kwak ,  Hyun-Soon Jang ,  Jae-Hoon Joo ,  Seung-Whan Seo ,  Jong-Hyoung Lim

    IPC分类号： G01R31/3177 ,  G06F11/25

    CPC分类号： G11C29/56 ,  G11C29/56008 ,  G11C2029/2602 ,  G11C2029/5602

    摘要： A semiconductor memory device includes a memory core unit, N data output buffers, N data output ports, and a plurality of test logic circuits. The memory core unit stores test data through N data lines. The N data output buffers are respectively connected to the corresponding N data lines. The N data output ports are connected to the corresponding N data output buffers, and exchange the test data with an external tester respectively. The plurality of test logic circuits receives the test data through the K data lines from the N data lines, performs test logic operation on the received test data, and provides a data output buffer control signal that determines activation of K data output buffers of the N data output buffers in test mode. The semiconductor memory device reduces test cycle.

    摘要翻译： 半导体存储器件包括存储器核心单元，N个数据输出缓冲器，N个数据输出端口以及多个测试逻辑电路。 存储核心单元通过N条数据线存储测试数据。 N个数据输出缓冲器分别连接到相应的N个数据线。 N个数据输出端口连接到相应的N个数据输出缓冲器，并分别与外部测试仪交换测试数据。 多个测试逻辑电路通过来自N条数据线的K条数据线接收测试数据，对所接收的测试数据进行测试逻辑运算，并提供一个数据输出缓冲器控制信号，该信号确定N个数据输出缓冲器的激活 测试模式下的数据输出缓冲区。 半导体存储器件降低了测试周期。

    Voltage clamping circuit for semiconductor devices
    6.
    发明授权
    Voltage clamping circuit for semiconductor devices 失效
    半导体器件钳位电路

    公开(公告)号：US5914626A

    公开(公告)日：1999-06-22

    申请号：US770627

    申请日：1996-12-19

    申请人： Hong-Beom Kim ,  Sang-Seok Kang ,  Byung-Heon Kwak ,  Yong-Jin Park

    发明人： Hong-Beom Kim ,  Sang-Seok Kang ,  Byung-Heon Kwak ,  Yong-Jin Park

    IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04 ,  H03K5/003 ,  H03K5/007 ,  H03K5/08

    CPC分类号： H03K5/003

    摘要： A voltage clamping circuit for a semiconductor memory device which is capable of rapidly coping with the demand of the user. The voltage clamping circuit includes PMOS transistors connected in series between an external supply voltage terminal and a node on an output line of a DC voltage generator, a control PMOS transistor having a channel connected at both ends thereof respectively to the node on the output line and a node between the second and third ones of the series-connected PMOS transistors, and a pad connected to a control electrode of the control PMOS transistor. The pad is selectively connected to a supply voltage in a first state and to a ground voltage in a second state, thereby controlling a clamping interval of the clamping means to be variable. The first state is a state requiring a longer clamping interval than that of the second state.

    摘要翻译： 一种用于半导体存储器件的电压钳位电路，其能够快速地应对用户的需求。 电压钳位电路包括串联连接在直流电压发生器的输出线上的外部电源电压端子与节点之间的PMOS晶体管，其两端分别连接到输出线路上的节点的控制PMOS晶体管，以及 串联连接的PMOS晶体管中的第二和第三个之间的节点，以及连接到控制PMOS晶体管的控制电极的焊盘。 焊盘选择性地连接到处于第一状态的电源电压和第二状态的接地电压，由此控制夹紧装置的夹紧间隔是可变的。 第一状态是需要比第二状态更长的夹持间隔的状态。