公开(公告)号：US08742466B2

公开(公告)日：2014-06-03

申请号：US12953748

申请日：2010-11-24

申请人： Jae-Joo Shim ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Woojin Cho

发明人： Jae-Joo Shim ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Woojin Cho

IPC分类号： H01L23/52

CPC分类号： H01L23/3157 ,  H01L21/76816 ,  H01L23/291 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.

摘要翻译： 提供一种三维半导体器件及其制造方法。 三维半导体器件可以包括用于提供间隙区域的模具结构和包括设置在间隙区域中的多个互连图案的互连结构。 模具结构可以包括限定互连图案的上表面和下表面的层间模具和限定层间模具下面的互连图案的侧壁的侧壁模具。

公开(公告)号：US08592912B2

公开(公告)日：2013-11-26

申请号：US13106481

申请日：2011-05-12

申请人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Jae-Joo Shim

发明人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Jae-Joo Shim

IPC分类号： H01L29/78

CPC分类号： H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a plurality of conductive patterns stacked on a substrate and spaced apart from each other and a pad pattern including a flat portion extending in a first direction parallel to the substrate from one end of any one of the plurality of conductive patterns, and a landing sidewall portion extending upward from a top surface of the flat portion, wherein a width of a portion of the landing sidewall portion in a second direction parallel to the substrate and perpendicular to the first direction is less than a width of the flat portion.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括：多个导电图案，其堆叠在基板上并彼此间隔开;以及焊盘图案，其包括从多个导电图案中的任一个的一端平行于基板延伸的平坦部分， 以及从所述平坦部分的顶表面向上延伸的着陆侧壁部分，其中所述着陆侧壁部分在平行于所述基板并且垂直于所述第一方向的第二方向上的一部分的宽度小于所述平坦部分的宽度 。

公开(公告)号：US09111799B2

公开(公告)日：2015-08-18

申请号：US13109230

申请日：2011-05-17

申请人： Sung-Min Hwang ,  Kyoung-Hoon Kim ,  Hansoo Kim ,  Jae-Joo Shim ,  Jaehoon Jang ,  Wonseok Cho ,  Byoungkeun Son ,  Hoosung Cho

发明人： Sung-Min Hwang ,  Kyoung-Hoon Kim ,  Hansoo Kim ,  Jae-Joo Shim ,  Jaehoon Jang ,  Wonseok Cho ,  Byoungkeun Son ,  Hoosung Cho

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/66

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate doped with a first conductive type dopant, a plurality of stacked structures arranged side by side on the substrate and extending in a first direction, each of the stacked structures including gate electrodes spaced apart from each other, the plurality of stacked structures including a pair of stacked structures spaced apart from each other at a first interval in a second direction perpendicular to the first direction, and a pick-up region extending in the first direction in the substrate between the pair of stacked structures and doped with the first conductive type dopant.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括掺杂有第一导电型掺杂剂的衬底，并且在衬底上并排布置并沿第一方向延伸的多个堆叠结构，每个堆叠结构包括彼此间隔开的栅电极， 堆叠结构，包括一对堆叠结构，其在垂直于第一方向的第二方向上以第一间隔彼此间隔开;以及拾取区域，在所述一对堆叠结构中的衬底中沿第一方向延伸并掺杂 第一导电型掺杂剂。

公开(公告)号：US20110291172A1

公开(公告)日：2011-12-01

申请号：US13109230

申请日：2011-05-17

申请人： Sung-Min Hwang ,  Kyoung-Hoon Kim ,  Hansoo Kim ,  Jae-Joo Shim ,  Jaehoon Jang ,  Wonseok Cho ,  Byoungkeun Son ,  Hoosung Cho

发明人： Sung-Min Hwang ,  Kyoung-Hoon Kim ,  Hansoo Kim ,  Jae-Joo Shim ,  Jaehoon Jang ,  Wonseok Cho ,  Byoungkeun Son ,  Hoosung Cho

IPC分类号： H01L29/78

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate doped with a first conductive type dopant, a plurality of stacked structures arranged side by side on the substrate and extending in a first direction, each of the stacked structures including gate electrodes spaced apart from each other, the plurality of stacked structures including a pair of stacked structures spaced apart from each other at a first interval in a second direction perpendicular to the first direction, and a pick-up region extending in the first direction in the substrate between the pair of stacked structures and doped with the first conductive type dopant.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括掺杂有第一导电型掺杂剂的衬底，并且在衬底上并排布置并沿第一方向延伸的多个堆叠结构，每个堆叠结构包括彼此间隔开的栅电极， 堆叠结构，包括一对堆叠结构，其在垂直于第一方向的第二方向上以第一间隔彼此间隔开;以及拾取区域，在所述一对堆叠结构中的衬底中沿第一方向延伸并掺杂 第一导电型掺杂剂。

公开(公告)号：US20120061744A1

公开(公告)日：2012-03-15

申请号：US13229136

申请日：2011-09-09

申请人： SUNG-MIN HWANG ,  Hansoo Kim ,  Changseok Kang ,  Wonseok Cho ,  Jae-Joo Shim

发明人： SUNG-MIN HWANG ,  Hansoo Kim ,  Changseok Kang ,  Wonseok Cho ,  Jae-Joo Shim

IPC分类号： H01L27/105

CPC分类号： H01L27/11578 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582

摘要： Three dimensional semiconductor memory devices are provided. The three dimensional semiconductor memory device includes a first stacked structure and a second stacked structure sequentially stacked on a substrate. The first stacked structure includes first insulating patterns and first gate patterns which are alternately and repeatedly stacked on a substrate, and the second stacked structure includes second insulating patterns and second gate patterns which are alternately and repeatedly stacked on the first stacked structure. A plurality of first vertical active patterns penetrate the first stacked structure, and a plurality of second vertical active patterns penetrate the second stacked structure. The number of the first vertical active patterns is greater than the number of the second vertical active patterns.

摘要翻译： 提供三维半导体存储器件。 三维半导体存储器件包括顺序层叠在基板上的第一堆叠结构和第二堆叠结构。 第一堆叠结构包括在衬底上交替重复堆叠的第一绝缘图案和第一栅极图案，并且第二堆叠结构包括在第一堆叠结构上交替重复堆叠的第二绝缘图案和第二栅极图案。 多个第一垂直有源图案穿透第一堆叠结构，并且多个第二垂直有源图案穿透第二堆叠结构。 第一垂直有源图案的数量大于第二垂直有效图案的数量。

公开(公告)号：US20120322252A1

公开(公告)日：2012-12-20

申请号：US13594102

申请日：2012-08-24

申请人： Byoungkeun SON ,  Hansoo Kim ,  Youngsoo An ,  Mingu Kim ,  Jinho Kim ,  Jaehyoung Choi ,  Sukhun Choi ,  Jae-Joo Shim ,  Wonseok Cho ,  Sunil Shim ,  Ju-Young Lim

发明人： Byoungkeun SON ,  Hansoo Kim ,  Youngsoo An ,  Mingu Kim ,  Jinho Kim ,  Jaehyoung Choi ,  Sukhun Choi ,  Jae-Joo Shim ,  Wonseok Cho ,  Sunil Shim ,  Ju-Young Lim

IPC分类号： H01L21/336

CPC分类号： H01L27/0207 ,  G11C7/18 ,  H01L23/535 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

摘要翻译： 半导体存储器件包括基本上平面的衬底; 垂直于衬底的存储器串，所述存储器串包括多个存储单元; 和多个细长字线，每个字线包括基本上平行于衬底并连接到存储器串的第一部分和相对于衬底基本上倾斜并在衬底上延伸的第二部分，其中多个 字线电连接到设置在存储器串的第一侧的第一导线，并且多个字线的第二组电连接到设置在存储器串的第二侧的第二导电线。

公开(公告)号：US08809938B2

公开(公告)日：2014-08-19

申请号：US13229136

申请日：2011-09-09

申请人： Sung-Min Hwang ,  Hansoo Kim ,  Changseok Kang ,  Wonseok Cho ,  Jae-Joo Shim

发明人： Sung-Min Hwang ,  Hansoo Kim ,  Changseok Kang ,  Wonseok Cho ,  Jae-Joo Shim

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/108

CPC分类号： H01L27/11578 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582

摘要： Three dimensional semiconductor memory devices are provided. The three dimensional semiconductor memory device includes a first stacked structure and a second stacked structure sequentially stacked on a substrate. The first stacked structure includes first insulating patterns and first gate patterns which are alternately and repeatedly stacked on a substrate, and the second stacked structure includes second insulating patterns and second gate patterns which are alternately and repeatedly stacked on the first stacked structure. A plurality of first vertical active patterns penetrate the first stacked structure, and a plurality of second vertical active patterns penetrate the second stacked structure. The number of the first vertical active patterns is greater than the number of the second vertical active patterns.

摘要翻译： 提供三维半导体存储器件。 三维半导体存储器件包括顺序层叠在基板上的第一堆叠结构和第二堆叠结构。 第一堆叠结构包括在衬底上交替重复堆叠的第一绝缘图案和第一栅极图案，并且第二堆叠结构包括在第一堆叠结构上交替重复堆叠的第二绝缘图案和第二栅极图案。 多个第一垂直有源图案穿透第一堆叠结构，并且多个第二垂直有源图案穿透第二堆叠结构。 第一垂直有源图案的数量大于第二垂直有效图案的数量。

公开(公告)号：US08787082B2

公开(公告)日：2014-07-22

申请号：US13594102

申请日：2012-08-24

申请人： Byoungkeun Son ,  Hansoo Kim ,  Youngsoo An ,  Mingu Kim ,  Jinho Kim ,  Jaehyoung Choi ,  Sukhun Choi ,  Jae-Joo Shim ,  Wonseok Cho ,  Sunil Shim ,  Ju-Young Lim

发明人： Byoungkeun Son ,  Hansoo Kim ,  Youngsoo An ,  Mingu Kim ,  Jinho Kim ,  Jaehyoung Choi ,  Sukhun Choi ,  Jae-Joo Shim ,  Wonseok Cho ,  Sunil Shim ,  Ju-Young Lim

IPC分类号： G11C16/04

CPC分类号： H01L27/0207 ,  G11C7/18 ,  H01L23/535 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

摘要翻译： 半导体存储器件包括基本上平面的衬底; 垂直于衬底的存储器串，所述存储器串包括多个存储单元; 和多个细长字线，每个字线包括基本上平行于衬底并连接到存储器串的第一部分和相对于衬底基本上倾斜并在衬底上延伸的第二部分，其中多个 字线电连接到设置在存储器串的第一侧的第一导线，并且多个字线的第二组电连接到设置在存储器串的第二侧的第二导电线。

公开(公告)号：US08284601B2

公开(公告)日：2012-10-09

申请号：US12752485

申请日：2010-04-01

申请人： Byoungkeun Son ,  Hansoo Kim ,  Youngsoo An ,  Mingu Kim ,  Jinho Kim ,  Jaehyoung Choi ,  Sukhun Choi ,  Jae-Joo Shim ,  Wonseok Cho ,  Sunil Shim ,  Ju-Young Lim

发明人： Byoungkeun Son ,  Hansoo Kim ,  Youngsoo An ,  Mingu Kim ,  Jinho Kim ,  Jaehyoung Choi ,  Sukhun Choi ,  Jae-Joo Shim ,  Wonseok Cho ,  Sunil Shim ,  Ju-Young Lim

IPC分类号： G11C16/04

CPC分类号： H01L27/0207 ,  G11C7/18 ,  H01L23/535 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a substantially planar substrate, a memory string vertical to the substrate, the memory string comprising a plurality of storage cells, and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

摘要翻译： 半导体存储器件包括基本上平面的衬底，垂直于衬底的存储器串，存储串包括多个存储单元，以及多个细长字线，每个字线包括基本上平行于衬底的第一部分， 到存储器串和相对于衬底基本上倾斜并在衬底上延伸的第二部分，其中多个字线中的第一组电连接到设置在存储器串的第一侧的第一导电线，以及第二组 多个字线的组电连接到设置在存储器串的第二侧的第二导线。

公开(公告)号：US20100254191A1

公开(公告)日：2010-10-07

申请号：US12752485

申请日：2010-04-01

申请人： Byoungkeun Son ,  Hansoo Kim ,  Youngsoo An ,  Mingu Kim ,  Jinho Kim ,  Jaehyoung Choi ,  Sukhun Choi ,  Jae-Joo Shim ,  Wonseok Cho ,  Sunil Shim ,  Ju-Young Lim

发明人： Byoungkeun Son ,  Hansoo Kim ,  Youngsoo An ,  Mingu Kim ,  Jinho Kim ,  Jaehyoung Choi ,  Sukhun Choi ,  Jae-Joo Shim ,  Wonseok Cho ,  Sunil Shim ,  Ju-Young Lim

IPC分类号： G11C16/02 ,  H01L21/3205

CPC分类号： H01L27/0207 ,  G11C7/18 ,  H01L23/535 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

摘要翻译： 半导体存储器件包括基本上平面的衬底; 垂直于衬底的存储器串，所述存储器串包括多个存储单元; 以及多个细长字线，每个字线包括基本上平行于衬底并连接到存储器串的第一部分和相对于衬底基本上倾斜并在衬底上方延伸的第二部分，其中多个 字线电连接到设置在存储器串的第一侧的第一导线，并且多个字线的第二组电连接到设置在存储器串的第二侧的第二导电线。