公开(公告)号：US20160027506A1

公开(公告)日：2016-01-28

申请号：US14878629

申请日：2015-10-08

申请人： Jae-Kyu Lee ,  Dae-Won Kim

发明人： Jae-Kyu Lee ,  Dae-Won Kim

IPC分类号： G11C13/00

CPC分类号： G11C13/004 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1677 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/76 ,  G11C2213/79

摘要： Memory systems can include a memory device having an array of nonvolatile memory cells therein, which is electrically coupled to a plurality of bit lines and a plurality of word lines. The nonvolatile memory cells may include respective nonvolatile resistive devices electrically coupled in series with corresponding cell transistors. A controller is also provided, which may be coupled to the memory device. The controller can be configured to drive the memory device with signals that support dual programming of: (i) the nonvolatile resistive devices; and (ii) interface states within the cell transistors, during operations to write data into the memory device.

公开(公告)号：US09183931B2

公开(公告)日：2015-11-10

申请号：US14337313

申请日：2014-07-22

申请人： Jae-Kyu Lee ,  Dae-Won Kim

发明人： Jae-Kyu Lee ,  Dae-Won Kim

IPC分类号： G11C11/00 ,  G11C11/14 ,  G11C11/15 ,  G11C13/00 ,  G11C11/16

CPC分类号： G11C13/004 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1677 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/76 ,  G11C2213/79

摘要： Memory systems can include a memory device having an array of nonvolatile memory cells therein, which is electrically coupled to a plurality of bit lines and a plurality of word lines. The nonvolatile memory cells may include respective nonvolatile resistive devices electrically coupled in series with corresponding cell transistors. A controller is also provided, which may be coupled to the memory device. The controller can be configured to drive the memory device with signals that support dual programming of: (i) the nonvolatile resistive devices; and (ii) interface states within the cell transistors, during operations to write data into the memory device.

摘要翻译： 存储器系统可以包括其中具有非易失性存储器单元的阵列的存储器件，其被电耦合到多个位线和多个字线。 非易失性存储单元可以包括与相应的单元晶体管串联电耦合的各自的非易失性电阻器件。 还提供了可以耦合到存储器件的控制器。 该控制器可以被配置为利用支持双重编程的信号来驱动存储器件：（i）非易失性电阻器件; 以及（ii）在将数据写入存储器件的操作期间，单元晶体管内的接口状态。

公开(公告)号：US20150155037A1

公开(公告)日：2015-06-04

申请号：US14337313

申请日：2014-07-22

申请人： Jae-Kyu Lee ,  Dae-Won Kim

发明人： Jae-Kyu Lee ,  Dae-Won Kim

IPC分类号： G11C13/00

CPC分类号： G11C13/004 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1677 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/76 ,  G11C2213/79

摘要： Memory systems can include a memory device having an array of nonvolatile memory cells therein, which is electrically coupled to a plurality of bit lines and a plurality of word lines. The nonvolatile memory cells may include respective nonvolatile resistive devices electrically coupled in series with corresponding cell transistors. A controller is also provided, which may be coupled to the memory device. The controller can be configured to drive the memory device with signals that support dual programming of: (i) the nonvolatile resistive devices; and (ii) interface states within the cell transistors, during operations to write data into the memory device.

摘要翻译： 存储器系统可以包括其中具有非易失性存储器单元的阵列的存储器件，其被电耦合到多个位线和多个字线。 非易失性存储单元可以包括与相应的单元晶体管串联电耦合的各自的非易失性电阻器件。 还提供了可以耦合到存储器件的控制器。 该控制器可以被配置为利用支持双重编程的信号来驱动存储器件：（i）非易失性电阻器件; 以及（ii）在将数据写入存储器件的操作期间，单元晶体管内的接口状态。

公开(公告)号：US07521767B2

公开(公告)日：2009-04-21

申请号：US10227343

申请日：2002-08-26

申请人： Jae-Kyu Lee ,  Jae-Goo Lee

发明人： Jae-Kyu Lee ,  Jae-Goo Lee

IPC分类号： H01L29/76

CPC分类号： H01L29/41783 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/41775

摘要： Methods of forming a MOS transistor and a MOS transistor fabricated thereby are provided. The MOS transistor includes a semiconductor substrate of a first conductivity type, and an insulated gate pattern having sidewalls disposed on a predetermined region of the semiconductor substrate of a first conductivity type so that portions of the semiconductor substrate of a first conductivity type on at least one side of the insulated gate pattern remain uncovered by the insulated gate pattern. The MOS transistor also includes impurity regions having at least an upper surface of a second conductivity type disposed on the semiconductor substrate at at least one side of the insulated gate pattern, as well as at least one spacer disposed on at least one sidewall of the insulated gate pattern. The MOS transistor further contains a pad of a second conductivity type disposed on an upper surface of the impurity regions, whereby the pad covers a lower portion of the at least one spacer.

摘要翻译： 提供了形成MOS晶体管和由此制造的MOS晶体管的方法。 MOS晶体管包括第一导电类型的半导体衬底和具有设置在第一导电类型的半导体衬底的预定区域上的侧壁的绝缘栅极图案，使得在至少一个第一导电类型上的第一导电类型的半导体衬底的部分 绝缘栅极图案的一侧保持未被绝缘栅极图案覆盖。 MOS晶体管还包括在绝缘栅极图案的至少一侧具有至少设置在半导体衬底上的第二导电类型的上表面的杂质区域，以及设置在绝缘栅极图案的至少一个侧壁上的至少一个间隔物 门模式。 MOS晶体管还包含布置在杂质区的上表​​面上的第二导电类型的焊盘，由此焊盘覆盖至少一个间隔物的下部。

公开(公告)号：US07864124B2

公开(公告)日：2011-01-04

申请号：US12136929

申请日：2008-06-11

申请人： Suk-Chan Hong ,  Jae-Kyu Lee ,  Jun-Chul Kang

发明人： Suk-Chan Hong ,  Jae-Kyu Lee ,  Jun-Chul Kang

IPC分类号： H01Q1/24

CPC分类号： H01Q1/243 ,  H01Q5/40 ,  H01Q9/0421 ,  H01Q9/42 ,  H01Q21/30

摘要： A mobile phone includes a multi-band antenna which is mutually connected in a dependent manner for operation according to a signal transmitted to and received from the mobile phone; and a resonance unit for generating resonance for multiple frequency bands as ends of the multi-band antenna are spaced apart at a predetermined interval, to improve mute performance, reduce SAR, and prevent a reduction in call performance due to an influence of a user's body and hand when holding the mobile phone to make a call.

摘要翻译： 移动电话包括：多频带天线，其以依赖方式相互连接，用于根据发送给移动电话并从移动电话接收的信号进行操作; 并且用于产生作为多频带天线的端部的多个频带的谐振的谐振单元以预定间隔隔开，以改善静音性能，降低SAR，并且防止由于用户身体的影响而引起的呼叫性能的降低 手持手机拨打电话。

公开(公告)号：US08203454B2

公开(公告)日：2012-06-19

申请号：US12396402

申请日：2009-03-02

申请人： Heather-Marie Callanan Knight ,  Jae-Kyu Lee ,  Hongshen Ma ,  Lauren Kattany

发明人： Heather-Marie Callanan Knight ,  Jae-Kyu Lee ,  Hongshen Ma ,  Lauren Kattany

IPC分类号： G08B23/00

CPC分类号： G08B21/0453 ,  G08B21/0469

摘要： A wheelchair alarm system and method for preventing falls for patients at risk by recognizing the gesture of a patient attempting to stand. The wheelchair alarm system uses an array of proximity sensors and pressure sensors to create a map of the patient's sitting position, and then uses gesture recognition algorithms to determine when a patient is attempting to stand up. The wheelchair alarm system responds with light and voice alarms that can encourage the patient to remain seated and/or to make use of the system's integrated nurse-call function. The wheelchair alarm system can be seamlessly integrated into existing hospital WiFi networks, sending messages to the nurse call system as well as providing the patient's location.

摘要翻译： 一种轮椅警报系统和方法，用于通过识别试图站立的患者的手势来防止处于危险中的患者的跌倒。 轮椅警报系统使用一系列接近传感器和压力传感器来创建患者坐姿的映射，然后使用手势识别算法来确定患者何时尝试站起来。 轮椅警报系统响应轻便和语音警报，可以鼓励患者保持坐姿和/或利用系统的综合护士呼叫功能。 轮椅报警系统可以无缝集成到现有的医院WiFi网络中，向护士呼叫系统发送消息以及提供病人的位置。

公开(公告)号：US06329249B1

公开(公告)日：2001-12-11

申请号：US09333574

申请日：1999-06-15

申请人： Won-Suk Yang ,  Ki-Nam Kim ,  Jai-Hoon Sim ,  Jae-Kyu Lee

发明人： Won-Suk Yang ,  Ki-Nam Kim ,  Jai-Hoon Sim ,  Jae-Kyu Lee

IPC分类号： H01L218234

CPC分类号： H01L27/10844 ,  H01L21/823462

摘要： A method for fabricating a semiconductor device with different gate oxide layers. Oxidation is controlled in accordance with the active area dimension so that oxide grows thin at a wider active width (peripheral region) and grows thickly at a narrower active width (cell array region). A gate pattern is formed on a semiconductor substrate having different active areas. Gate spacers are formed and then active dimension dependent oxidation process is performed to grow the oxide layers differently from one another.

摘要翻译： 一种制造具有不同栅氧化层的半导体器件的方法。 根据有源面积尺寸控制氧化，使得氧化物在较宽的有源宽度（周边区域）上生长较薄，并且以较窄的有效宽度（电池阵列区域）厚厚地生长。 在具有不同有源区的半导体衬底上形成栅极图案。 形成栅极隔离物，然后进行活性尺寸依赖氧化工艺以使氧化物层彼此不同地生长。

公开(公告)号：US09165646B2

公开(公告)日：2015-10-20

申请号：US14047537

申请日：2013-10-07

申请人： Jae-Kyu Lee

发明人： Jae-Kyu Lee

IPC分类号： G11C11/15 ,  G11C13/00 ,  G11C11/16 ,  G11C5/04 ,  G11C11/00 ,  G11C16/04

CPC分类号： G11C13/004 ,  G11C5/04 ,  G11C11/005 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/0433 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/79

摘要： A resistive memory device includes a memory cell array, an input/output (I/O) sense amplifier unit, an address input buffer, a row decoder, and a column decoder. The memory cell array includes unit memory cells, and operates in response to a word line driving signal and a column selecting signal, each unit memory cell includes a resistive device and a compensation resistive device. The I/O sense amplifier unit amplifies data output from the memory cell array to generate first data, and transfers input data to the memory cell array. The address input buffer generates a row address signal and a column address signal based on an external address. The row decoder decodes the row address signal and generates the word line driving signal based on the decoded row address signal. The column decoder decodes the column address signal and generates the column selecting signal based on the decoded column address signal.

摘要翻译： 电阻式存储器件包括存储单元阵列，输入/输出（I / O）读出放大器单元，地址输入缓冲器，行解码器和列译码器。 存储单元阵列包括单元存储单元，并且响应于字线驱动信号和列选择信号而工作，每个单元存储单元包括电阻器件和补偿电阻器件。 I / O读出放大器单元放大从存储单元阵列输出的数据以产生第一数据，并将输入数据传送到存储单元阵列。 地址输入缓冲器基于外部地址生成行地址信号和列地址信号。 行解码器解码行地址信号，并基于解码的行地址信号产生字线驱动信号。 列解码器解码列地址信号，并根据解码的列地址信号产生列选择信号。

公开(公告)号：US08664634B2

公开(公告)日：2014-03-04

申请号：US13599259

申请日：2012-08-30

申请人： Hyun-Ju Lee ,  Jae-Kyu Lee

发明人： Hyun-Ju Lee ,  Jae-Kyu Lee

IPC分类号： H01L27/105 ,  H01L29/12

CPC分类号： H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： A resistive memory device may include a substrate, gate electrode structures, a first impurity region, a second impurity region, a first metal silicide pattern and a second metal silicide pattern. The substrate may have a first region where isolation patterns and first active patterns may be alternately arranged in a first direction, and a second region where linear second active patterns may be extended in the first direction. The gate electrode structures may be arranged between the first region and the second region of the substrate. The first and second impurity regions may be formed in the first and second impurity regions. The first metal silicide pattern may have an isolated shape configured to make contact with an upper surface of the first impurity region. The second metal silicide pattern may make contact with an upper surface of the second impurity region.

摘要翻译： 电阻式存储器件可以包括衬底，栅电极结构，第一杂质区，第二杂质区，第一金属硅化物图案和第二金属硅化物图案。 衬底可以具有其中隔离图案和第一有源图案可以沿第一方向交替布置的第一区域，以及可以在第一方向上延伸线性第二有源图案的第二区域。 栅极电极结构可以布置在衬底的第一区域和第二区域之间。 第一和第二杂质区可以形成在第一和第二杂质区中。 第一金属硅化物图案可以具有被配置为与第一杂质区的上表​​面接触的隔离形状。 第二金属硅化物图案可以与第二杂质区域的上表面接触。

公开(公告)号：US06955972B2

公开(公告)日：2005-10-18

申请号：US10457910

申请日：2003-06-10

申请人： Jae-Kyu Lee ,  Sang-Hyeon Lee

发明人： Jae-Kyu Lee ,  Sang-Hyeon Lee

IPC分类号： H01L21/76 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10897 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/763

摘要： Methods of fabricating integrated circuit devices include forming a trench in a face of an integrated circuit substrate. The trench has a trench sidewall and a trench floor. The method further including forming a first insulating layer on the trench sidewall that exposes at least part of the trench floor and forming a conductive plug in the trench on the trench floor. The conductive plug is electrically connected to the substrate at the trench floor through the trench sidewall that exposes the at least part of the trench floor. The conductive plug also has a plug top opposite the trench floor that is recessed beneath the face of the substrate. The method further includes forming a second insulating layer on the plug top.

摘要翻译： 制造集成电路器件的方法包括在集成电路衬底的表面形成沟槽。 沟槽具有沟槽侧壁和沟槽底板。 所述方法还包括在所述沟槽侧壁上形成第一绝缘层，所述第一绝缘层暴露所述沟槽底板的至少一部分并且在所述沟槽底板上的所述沟槽中形成导电插塞。 导电插塞通过沟槽侧壁电解连接到沟槽底板处的衬底，所述沟槽侧壁暴露出沟槽底板的至少部分。 导电插头还具有与沟槽底板相对的插头顶部，其凹陷在基板的表面下方。 该方法还包括在插头顶上形成第二绝缘层。