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    Non-volatile memory device and method of manufacturing the same
    1.
    发明授权
    Non-volatile memory device and method of manufacturing the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US07259430B2

    公开(公告)日：2007-08-21

    申请号：US11073134

    申请日：2005-03-04

    申请人： Jae-Man Yoon ,  Tae-Yong Kim ,  Dong-Gun Park ,  Choong-Ho Lee

    发明人： Jae-Man Yoon ,  Tae-Yong Kim ,  Dong-Gun Park ,  Choong-Ho Lee

    IPC分类号： H01L29/94

    CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7851

    摘要： A non-volatile memory device includes a fin body protruded from a semiconductor substrate. The fin body has first and second side surfaces opposite to each other. An inner dielectric layer pattern is formed on an upper surface, and the first and second side surfaces of the fin body. A floating gate electrode is formed on the inner dielectric layer pattern. The floating gate electrode has an uneven upper surface. An outer dielectric layer is formed on the floating gate electrode. A control gate electrode is formed on the outer dielectric layer.

    摘要翻译： 非易失性存储器件包括从半导体衬底突出的翅片体。 翅片体具有彼此相对的第一和第二侧表面。 在上表面以及翅片体的第一和第二侧表面上形成内部电介质层图案。 在内部电介质层图案上形成浮栅电极。 浮栅电极具有不均匀的上表面。 外电介质层形成在浮栅电极上。 控制栅电极形成在外电介质层上。

    Transistor and method of forming the same
    3.
    发明授权
    Transistor and method of forming the same 有权
    晶体管及其形成方法

    公开(公告)号：US07919378B2

    公开(公告)日：2011-04-05

    申请号：US12397176

    申请日：2009-03-03

    申请人： Jae-Man Yoon ,  Choong-Ho Lee ,  Dong-Gun Park ,  Chul Lee

    发明人： Jae-Man Yoon ,  Choong-Ho Lee ,  Dong-Gun Park ,  Chul Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage.

    摘要翻译： 根据本发明的一些实施例，鳍型晶体管包括与硅衬底一体形成的有源结构。 活性结构包括在源极/漏极区域下形成阻挡区的沟槽。 栅极结构形成为跨越有源结构的上表面并且覆盖有源结构的侧部的暴露的侧表面。 可以充分确保翅片型晶体管的有效沟道长度，从而可以防止晶体管的短沟道效应，并且鳍式晶体管可能具有高击穿电压。

    Fin field effect transistor device and method of fabricating the same
    6.
    发明授权
    Fin field effect transistor device and method of fabricating the same 失效
    Fin场效应晶体管器件及其制造方法

    公开(公告)号：US07323375B2

    公开(公告)日：2008-01-29

    申请号：US11091457

    申请日：2005-03-28

    申请人： Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

    发明人： Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

    IPC分类号： H01L21/00

    CPC分类号： H01L29/7851 ,  H01L21/84 ,  H01L29/66795

    摘要： Methods of forming field effect transistors (FETs) having fin-shaped active regions include patterning a semiconductor substrate to define a fin-shaped semiconductor active region therein, which is surrounded by a trench. At least an upper portion of the fin-shaped semiconductor active region is covered with a sacrificial layer. This sacrificial layer is selectively etched-back to define sacrificial spacers on sidewalls of the fin-shaped semiconductor active region. The electrically insulating region is formed on the sacrificial spacers. The sacrificial spacers are then removed by selectively etching the sacrificial spacers using the electrically insulating region as an etching mask. An insulated gate electrode is then formed on the sidewalls of the fin-shaped semiconductor active region.

    摘要翻译： 形成具有鳍状有源区的场效应晶体管（FET）的方法包括图案化半导体衬底以在其中限定由沟槽包围的鳍状半导体有源区。 鳍形半导体有源区域的至少上部被牺牲层覆盖。 该牺牲层被有选择地回蚀刻以在鳍状半导体有源区域的侧壁上限定牺牲隔离物。 电绝缘区域形成在牺牲间隔物上。 然后通过使用电绝缘区域作为蚀刻掩模选择性地蚀刻牺牲隔离物来去除牺牲间隔物。 然后在鳍状半导体有源区的侧壁上形成绝缘栅电极。

    Method of operating a flash memory device
    7.
    发明授权
    Method of operating a flash memory device 失效
    操作闪存设备的方法

    公开(公告)号：US07177192B2

    公开(公告)日：2007-02-13

    申请号：US11274310

    申请日：2005-11-16

    申请人： Jae-Man Yoon ,  Eun-Suk Cho ,  Dong-Gun Park ,  Choong-Ho Lee

    发明人： Jae-Man Yoon ,  Eun-Suk Cho ,  Dong-Gun Park ,  Choong-Ho Lee

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

    摘要： A method of operating a NAND flash memory device that comprising a unit string comprising a string selection transistor connected to a bit line, a cell transistor connected to the string selection transistor, and a ground selection transistor connected to the cell transistor is provided. The method comprises applying a negative bias voltage to the string selection transistor and the ground selection transistor in a stand-by mode of the NAND flash memory device.

    摘要翻译： 提供一种操作NAND闪速存储器件的方法，该NAND闪速存储器件包括连接到位线的串选择晶体管，连接到串选择晶体管的单元晶体管和连接到单元晶体管的接地选择晶体管的单元串。 该方法包括在NAND闪速存储器件的待机模式中向串选择晶体管和接地选择晶体管施加负偏置电压。

    Fin field effect transistor device and method of fabricating the same
    8.
    发明申请
    Fin field effect transistor device and method of fabricating the same 失效
    Fin场效应晶体管器件及其制造方法

    公开(公告)号：US20050250285A1

    公开(公告)日：2005-11-10

    申请号：US11091457

    申请日：2005-03-28

    申请人： Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

    发明人： Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

    IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/786 ,  H01L29/94

    CPC分类号： H01L29/7851 ,  H01L21/84 ,  H01L29/66795

    摘要： Methods of forming field effect transistors (FETs) having fin-shaped active regions include patterning a semiconductor substrate to define a fin-shaped semiconductor active region therein, which is surrounded by a trench. At least an upper portion of the fin-shaped semiconductor active region is covered with a sacrificial layer. This sacrificial layer is selectively etched-back to define sacrificial spacers on sidewalls of the fin-shaped semiconductor active region. The electrically insulating region is formed on the sacrificial spacers. The sacrificial spacers are then removed by selectively etching the sacrificial spacers using the electrically insulating region as an etching mask. An insulated gate electrode is then formed on the sidewalls of the fin-shaped semiconductor active region.

    摘要翻译： 形成具有鳍状有源区的场效应晶体管（FET）的方法包括图案化半导体衬底以在其中限定由沟槽包围的鳍状半导体有源区。 鳍形半导体有源区域的至少上部被牺牲层覆盖。 该牺牲层被有选择地回蚀刻以在鳍状半导体有源区域的侧壁上限定牺牲隔离物。 电绝缘区域形成在牺牲间隔物上。 然后通过使用电绝缘区域作为蚀刻掩模选择性地蚀刻牺牲隔离物来去除牺牲间隔物。 然后在鳍状半导体有源区的侧壁上形成绝缘栅电极。

    Semiconductor device having a channel pattern and method of manufacturing the same
    10.
    发明授权
    Semiconductor device having a channel pattern and method of manufacturing the same 有权
    具有沟道图案的半导体器件及其制造方法

    公开(公告)号：US07579648B2

    公开(公告)日：2009-08-25

    申请号：US11183997

    申请日：2005-07-19

    申请人： Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

    发明人： Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

    IPC分类号： H01L27/108

    CPC分类号： H01L29/78696 ,  H01L29/66666 ,  H01L29/66772 ,  H01L29/78642

    摘要： A semiconductor device may include a tubular channel pattern vertically extending from a semiconductor substrate. A gate insulation layer may be provided on faces exposed through the channel pattern. A gate electrode may be provided on the gate insulation layer. The gate electrode may fill the channel pattern. A conductive region, which may serve as lower source/drain regions, may be formed at a surface portion of the semiconductor substrate. The conductive region may contact a lower portion of the channel pattern. A conductive pattern, which may serve as upper source/drain regions, may horizontally extend from an upper portion of the channel pattern.

    摘要翻译： 半导体器件可以包括从半导体衬底垂直延伸的管状沟道图案。 可以在通过通道图案暴露的面上设置栅极绝缘层。 栅极电极可以设置在栅极绝缘层上。 栅电极可以填充沟道图案。 可以在半导体衬底的表面部分处形成可用作下部源极/漏极区域的导电区域。 导电区域可以接触通道图案的下部。 可以用作上部源极/漏极区域的导电图案可以从沟道图案的上部部分水平延伸。