Voltage detecting circuit for semiconductor memory device
    1.
    发明授权
    Voltage detecting circuit for semiconductor memory device 失效
    半导体存储器件的电压检测电路

    公开(公告)号:US06456555B2

    公开(公告)日:2002-09-24

    申请号:US09747860

    申请日:2000-12-22

    CPC classification number: G11C8/08 G11C5/143 G11C11/4074

    Abstract: A voltage detecting circuit includes first and second reference voltage generating circuits. The first reference voltage generating circuit provides a reference voltage during a normal operation mode. The second reference voltage generating circuit provides a reference voltage during a test mode. A comparison voltage generating circuit is also included and provides a comparison voltage during both modes in response to a boosted voltage. A differential amplifier circuit is further included in the voltage detecting circuit. The differential amplifier generates an amplified difference signal that is used to generate a voltage level detection signal. The voltage level detection signal controls a pumping operation for generating the boosted voltage level. A bypass circuit may also be provided to lower a detected boosted voltage level and allow operation at lower voltage levels. The voltage detecting circuit according to this invention is unaffected by process and temperature variations and allows precise and stable voltage detection in either operation mode.

    Abstract translation: 电压检测电路包括第一和第二参考电压产生电路。 第一参考电压发生电路在正常操作模式期间提供参考电压。 第二参考电压产生电路在测试模式期间提供参考电压。 还包括比较电压发生电路,并且响应于升压电压在两种模式下提供比较电压。 差分放大电路还包括在电压检测电路中。 差分放大器产生用于产生电压电平检测信号的放大差分信号。 电压电平检测信号控制用于产生升压电压电平的泵浦操作。 还可以提供旁路电路以降低检测到的升压电压电平并允许在较低电压电平下操作。 根据本发明的电压检测电路不受过程和温度变化的影响,并且允许在任一操作模式下的精确和稳定的电压检测。

    Negative voltage generator for a semiconductor memory device
    3.
    发明申请
    Negative voltage generator for a semiconductor memory device 失效
    用于半导体存储器件的负电压发生器

    公开(公告)号:US20050030086A1

    公开(公告)日:2005-02-10

    申请号:US10940804

    申请日:2004-08-26

    CPC classification number: H02M3/07 G11C5/147 G11C16/30 H02M2003/071

    Abstract: A negative voltage generator is controlled responsive to a word line precharge signal. Voltage fluctuations in a negatively biased word line scheme are reduced by using a kicker circuit to provide a predetermined amount of negative charge to shut off a word line during a precharge operation. The negative voltage generator includes first and second negative charge pumps. The second charge pump is activated responsive to the word line precharge signal. A negative voltage regulator can be used to regulate a negative voltage signal. A level shifter uses two voltage dividers and a differential amplifier to reduce response time, output ripple, and sensitivity to process and temperature variations. A negative voltage regulator cancels ripple from a charge pump to provide a stable negative bias voltage and reduce the amount of charge needed to precharge a word line.

    Abstract translation: 响应于字线预充电信号控制负电压发生器。 负偏置字线方案中的电压波动通过使用提升电路来在预充电操作期间提供预定量的负电荷来关闭字线来减小。 负电压发生器包括第一和第二负电荷泵。 响应于字线预充电信号激活第二电荷泵。 负电压调节器可用于调节负电压信号。 电平移位器使用两个分压器和差分放大器来减少响应时间,输出纹波和对过程和温度变化的敏感性。 负电压调节器抵消来自电荷泵的纹波,以提供稳定的负偏置电压并减少预充电字线所需的电荷量。

    Temperature sensor and method for detecting trip temperature of a temperature sensor
    4.
    发明申请
    Temperature sensor and method for detecting trip temperature of a temperature sensor 有权
    用于检测温度传感器跳闸温度的温度传感器和方法

    公开(公告)号:US20050024097A1

    公开(公告)日:2005-02-03

    申请号:US10928498

    申请日:2004-08-30

    CPC classification number: G01K7/015 G01K3/005

    Abstract: A comparator circuit of a temperature sensor includes an output node and a variable current node. The output node is a first voltage at a given temperature when a current at the variable current node is less than a threshold current, and a different second voltage at the given temperature when the current at the variable current node is more than the threshold current. A variable resistance circuit includes at least n resistors of different resistive values connected in series between the variable current node of the comparator and a supply voltage, where n is an integer of 4 or more. A switching circuit is provided to selectively bypasses individual ones of the n resistors during a test sequence to determine a trip temperature of the sensor.

    Abstract translation: 温度传感器的比较器电路包括输出节点和可变电流节点。 当可变电流节点处的电流小于阈值电流时,输出节点是给定温度下的第一电压,以及当可变电流节点处的电流大于阈值电流时在给定温度下的不同的第二电压。 可变电阻电路包括串联连接在比较器的可变电流节点和电源电压之间的至少n个不同电阻值的电阻器,其中n是4或更大的整数。 提供开关电路以在测试序列期间选择性地旁路n个电阻器中的各个电阻器,以确定传感器的跳闸温度。

    Temperature sensor and method for detecting trip temperature of a temperature sensor
    5.
    发明授权
    Temperature sensor and method for detecting trip temperature of a temperature sensor 有权
    用于检测温度传感器跳闸温度的温度传感器和方法

    公开(公告)号:US07106127B2

    公开(公告)日:2006-09-12

    申请号:US10627693

    申请日:2003-07-28

    CPC classification number: G01K7/015 G01K3/005

    Abstract: A comparator circuit of a temperature sensor includes an output node and a variable current node. The output node is a first voltage at a given temperature when a current at the variable current node is less than a threshold current, and a different second voltage at the given temperature when the current at the variable current node is more than the threshold current. A variable resistance circuit includes at least n resistors of different resistive values connected in series between the variable current node of the comparator and a supply voltage, where n is an integer of 4 or more. A switching circuit is provided to selectively bypasses individual ones of the n resistors during a test sequence to determine a trip temperature of the sensor.

    Abstract translation: 温度传感器的比较器电路包括输出节点和可变电流节点。 当可变电流节点处的电流小于阈值电流时,输出节点是给定温度下的第一电压,以及当可变电流节点处的电流大于阈值电流时在给定温度下的不同的第二电压。 可变电阻电路包括串联连接在比较器的可变电流节点和电源电压之间的至少n个不同电阻值的电阻器,其中n是4或更大的整数。 提供开关电路以在测试序列期间选择性地旁路n个电阻器中的各个电阻器,以确定传感器的跳闸温度。

    Negative voltage generator for a semiconductor memory device

    公开(公告)号:US07023262B2

    公开(公告)日:2006-04-04

    申请号:US10940804

    申请日:2004-08-26

    CPC classification number: H02M3/07 G11C5/147 G11C16/30 H02M2003/071

    Abstract: A negative voltage generator is controlled responsive to a word line precharge signal. Voltage fluctuations in a negatively biased word line scheme are reduced by using a kicker circuit to provide a predetermined amount of negative charge to shut off a word line during a precharge operation. The negative voltage generator includes first and second negative charge pumps. The second charge pump is activated responsive to the word line precharge signal. A negative voltage regulator can be used to regulate a negative voltage signal. A level shifter uses two voltage dividers and a differential amplifier to reduce response time, output ripple, and sensitivity to process and temperature variations. A negative voltage regulator cancels ripple from a charge pump to provide a stable negative bias voltage and reduce the amount of charge needed to precharge a word line.

    Negative voltage generator for a semiconductor memory device
    7.
    发明授权
    Negative voltage generator for a semiconductor memory device 有权
    用于半导体存储器件的负电压发生器

    公开(公告)号:US07336121B2

    公开(公告)日:2008-02-26

    申请号:US09901930

    申请日:2001-07-09

    CPC classification number: G11C16/30 G11C5/147 H02M3/07 H02M2003/071

    Abstract: A negative voltage generator is controlled responsive to a word line precharge signal. Voltage fluctuations in a negatively biased word line scheme are reduced by using a kicker circuit to provide a predetermined amount of negative charge to shut off a word line during a precharge operation. The negative voltage generator includes first and second negative charge pumps. The second charge pump is activated responsive to the word line precharge signal. A negative voltage regulator can be used to regulate a negative voltage signal. A level shifter uses two voltage dividers and a differential amplifier to reduce response time, output ripple, and sensitivity to process and temperature variations. A negative voltage regulator cancels ripple from a charge pump to provide a stable negative bias voltage and reduce the amount of charge needed to precharge a word line.

    Abstract translation: 响应于字线预充电信号控制负电压发生器。 负偏置字线方案中的电压波动通过使用提升电路来在预充电操作期间提供预定量的负电荷来关闭字线来减小。 负电压发生器包括第一和第二负电荷泵。 响应于字线预充电信号激活第二电荷泵。 负电压调节器可用于调节负电压信号。 电平移位器使用两个分压器和差分放大器来减少响应时间,输出纹波和对过程和温度变化的敏感性。 负电压调节器抵消来自电荷泵的纹波,以提供稳定的负偏置电压并减少预充电字线所需的电荷量。

    Negatively biased word line scheme for a semiconductor memory device
    8.
    发明授权
    Negatively biased word line scheme for a semiconductor memory device 失效
    用于半导体存储器件的负偏置字线方案

    公开(公告)号:US06545923B2

    公开(公告)日:2003-04-08

    申请号:US09901785

    申请日:2001-07-09

    CPC classification number: G11C11/4085 G11C8/08

    Abstract: A memory device utilizing a negatively biased word line scheme diverts word line discharge current from the negative voltage source during a precharge operation, thereby reducing voltage fluctuations and current consumption from the negative voltage source. A main word line, sub-word line, word line enable signal, or other type of word line is coupled to the negative voltage source during a precharge operation. The word line is also coupled to a second power supply during the precharge operation, and then uncoupled from the second power supply after most of the word line discharge current has been diverted. The negative voltage source can then discharge and maintain the word line at a negative bias.

    Abstract translation: 利用负偏置字线方案的存储器件在预充电操作期间从负电压源转移字线放电电流,从而降低来自负电压源的电压波动和电流消耗。 在预充电操作期间,主字线,子字线,字线使能信号或其它类型的字线耦合到负电压源。 在预充电操作期间,字线还耦合到第二电源,然后在大部分字线放电电流被转移之后与第二电源分离。 然后,负电压源可以以负偏压放电并维持字线。

    Voltage detecting circuit for semiconductor memory device

    公开(公告)号:US06424578B1

    公开(公告)日:2002-07-23

    申请号:US09748350

    申请日:2000-12-22

    Abstract: A voltage detecting circuit includes a first voltage generator that provides a reference voltage, a second voltage generator that provides a comparison voltage in response to a boosted voltage, and a differential amplifier that provides an amplified difference signal to generate a voltage level detection signal in response to a voltage difference between the reference voltage and the comparison voltage. A bypass circuit is coupled to the amplified signal to detect a target VPP level suitable for a test mode by providing a current path in response to the comparison voltage when the comparison voltage reaches a predetermined level. The voltage detecting circuit thereby allows a precise and stable detecting operation to be performed regardless of the operation mode or process or temperature variations.

    Semiconductor memory device including a delaying circuit capable of generating a delayed signal with a substantially constant delay time
    10.
    发明授权
    Semiconductor memory device including a delaying circuit capable of generating a delayed signal with a substantially constant delay time 失效
    半导体存储器件包括能够产生具有基本恒定的延迟时间的延迟信号的延迟电路

    公开(公告)号:US06845049B2

    公开(公告)日:2005-01-18

    申请号:US10313817

    申请日:2002-12-05

    CPC classification number: G11C7/04 G11C7/06 G11C7/22 G11C7/227 G11C2207/2281

    Abstract: A semiconductor memory device with a bit line sense enable signal generating circuit is disclosed. The semiconductor memory device includes a word line selection signal generating circuit for generating a word line selection signal for selecting a word line; a delay circuit for generating a delayed signal by delaying a signal to the same extent of time period which is needed for the word line selection signal generating circuit to generate the word line selection signal; and a Schmitt trigger for generating a word line enable detecting signal by receiving an output signal from the delay circuit and that is connected to a power supply voltage which has the same voltage level as the voltage level used to enable the word line. The bit line sense enable signal generating circuit in the present invention occupies a relatively smaller layout area than that of conventional semiconductor memory devices. Furthermore, the generating circuit generates a bit line sense enable signal with constant delay time that is immune from process changes, voltage fluctuations, and temperature fluctuations.

    Abstract translation: 公开了一种具有位线检测使能信号发生电路的半导体存储器件。 半导体存储器件包括用于产生用于选择字线的字线选择信号的字线选择信号发生电路; 延迟电路,用于通过将信号延迟到所述字线选择信号发生电路产生字线选择信号所需的相同的时间周期来产生延迟信号; 以及施密特触发器,用于通过接收来自延迟电路的输出信号并连接到与用于使能字线的电压电平相同的电压电平的电源电压来产生字线使能检测信号。 本发明中的位线检测使能信号发生电路的布局面积比传统的半导体存储器件要小。 此外,发生电路产生具有恒定延迟时间的位线检测使能信号,其免受过程变化,电压波动和温度波动的影响。

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