公开(公告)号：US20060183296A1

公开(公告)日：2006-08-17

申请号：US11398536

申请日：2006-04-06

申请人： Jae-yoon Yoo ,  Moon-han Park ,  Dong-ho Ahn ,  Sug-hun Hong ,  Kyung-won Park ,  Jeong-soo Lee

发明人： Jae-yoon Yoo ,  Moon-han Park ,  Dong-ho Ahn ,  Sug-hun Hong ,  Kyung-won Park ,  Jeong-soo Lee

IPC分类号： H01L21/76

CPC分类号： H01L21/76232

摘要： An isolation method for a semiconductor device where an insulating mask layer is formed on desired regions of a semiconductor substrate. A trench is formed to a desired depth in the semiconductor substrate using the insulating mask layer as a mask. An oxide layer is formed on the insulating mask layer and on the sidewall of the trench. A trench liner layer is formed on the oxide layer. An insulating filler layer is formed in the trench in the semiconductor substrate, on which the trench liner layer is formed, so as to fill the trench. The insulating mask layer is removed. According to the isolation method for a semiconductor device, it is possible to reduce dents from occurring along the edge of the trench, reduce a bird's beak type oxide layer from occurring at an interface between the insulating mask layers, decrease the leakage current, or improve the electrical characteristics, such as threshold voltage.

公开(公告)号：US06486039B2

公开(公告)日：2002-11-26

申请号：US09933039

申请日：2001-08-21

申请人： Jae-yoon Yoo ,  Jeong-soo Lee ,  Nae-in Lee

发明人： Jae-yoon Yoo ,  Jeong-soo Lee ,  Nae-in Lee

IPC分类号： H01L21302

CPC分类号： H01L21/76229 ,  H01L21/76237

摘要： A method of fabricating a trench isolation structure in a high-density semiconductor device that provides an isolation characteristic that is independent of the properties of adjacent MOS transistor devices, wherein a first trench in a first isolation area and a second trench implanted are formed on a semiconductor substrate, a nitrogen (N)-rich silicon layer is formed on the sidewall in a second isolation area, a subsequent oxidation process may be employed to fabricate oxide layers, each having a different thickness, on the sidewall surfaces of the first and second trenches. When the first and second oxide-layered trenches are filled with a stress relief liner and a dielectric material, the different thicknesses of the oxides prevent leakage currents from flowing to an adjacent semiconductor device, regardless of the doping properties of each device.