公开(公告)号：US20090061567A1

公开(公告)日：2009-03-05

申请号：US12268919

申请日：2008-11-11

申请人： James C. Kemerling ,  David Ihme ,  William D. Cox

发明人： James C. Kemerling ,  David Ihme ,  William D. Cox

IPC分类号： H01L21/82

CPC分类号： H03K19/17736 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/17748 ,  H03K19/17796 ,  H01L2924/00

摘要： A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.

公开(公告)号：US07335966B2

公开(公告)日：2008-02-26

申请号：US10906527

申请日：2005-02-23

申请人： David Ihme ,  James C. Kemerling ,  William D. Cox

发明人： David Ihme ,  James C. Kemerling ,  William D. Cox

IPC分类号： H01L29/00

CPC分类号： H01G4/385 ,  H01L27/0805 ,  H01L2924/14 ,  H01L2924/00

摘要： A semiconductor device having a plurality of layers and a capacitor array that includes a plurality of individual capacitors. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections and capacitances of the plurality of individual capacitors in the capacitor array. The semiconductor device may include a metal structure disposed within the device to provide an electromagnetic shield for at least one of the plurality of individual capacitors in the capacitor array.

摘要翻译： 具有多个层的半导体器件和包括多个单独的电容器的电容器阵列。 半导体器件中的多个层中的至少一个可以是被配置为确定电容器阵列中的多个单独电容器的连接和电容的通孔层。 半导体器件可以包括设置在器件内的金属结构，以为电容器阵列中的多个独立电容器中的至少一个提供电磁屏蔽。

公开(公告)号：US20090032968A1

公开(公告)日：2009-02-05

申请号：US12246802

申请日：2008-10-07

申请人： James C. Kemerling ,  David Ihme ,  William D. Cox

发明人： James C. Kemerling ,  David Ihme ,  William D. Cox

IPC分类号： H01L23/522

CPC分类号： H03K19/17736 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/17748 ,  H03K19/17796 ,  H01L2924/00

摘要： A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.

摘要翻译： 具有多个层的半导体器件和布置在瓦片中的多个电路元件。 半导体器件中的多个层中的至少一个可以是经配置以确定多个电路元件的连接的通孔层。 半导体器件可以包括具有设置成互连多个电路元件的多个金属层的互连被子。 多个电路元件可以是模拟电路元件和/或数字电路元件。 瓦片可以是形成混合信号结构阵列的模拟瓦片和数字瓦片。

公开(公告)号：US07972907B2

公开(公告)日：2011-07-05

申请号：US12268919

申请日：2008-11-11

申请人： James C. Kemerling ,  David Ihme ,  William D. Cox

发明人： James C. Kemerling ,  David Ihme ,  William D. Cox

IPC分类号： H01L21/82

CPC分类号： H03K19/17736 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/17748 ,  H03K19/17796 ,  H01L2924/00

摘要： A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.

摘要翻译： 具有多个层的半导体器件和布置在瓦片中的多个电路元件。 半导体器件中的多个层中的至少一个可以是经配置以确定多个电路元件的连接的通孔层。 半导体器件可以包括具有设置成互连多个电路元件的多个金属层的互连被子。 多个电路元件可以是模拟电路元件和/或数字电路元件。 瓦片可以是形成混合信号结构阵列的模拟瓦片和数字瓦片。

公开(公告)号：US07626272B2

公开(公告)日：2009-12-01

申请号：US12246802

申请日：2008-10-07

申请人： James C. Kemerling ,  David Ihme ,  William D. Cox

发明人： James C. Kemerling ,  David Ihme ,  William D. Cox

IPC分类号： H01L23/12 ,  H01L23/52 ,  H01L29/40

CPC分类号： H03K19/17736 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/17748 ,  H03K19/17796 ,  H01L2924/00

摘要： A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.

摘要翻译： 具有多个层的半导体器件和布置在瓦片中的多个电路元件。 半导体器件中的多个层中的至少一个可以是经配置以确定多个电路元件的连接的通孔层。 半导体器件可以包括具有设置成互连多个电路元件的多个金属层的互连被子。 多个电路元件可以是模拟电路元件和/或数字电路元件。 瓦片可以是形成混合信号结构阵列的模拟瓦片和数字瓦片。

公开(公告)号：US07595229B2

公开(公告)日：2009-09-29

申请号：US11965069

申请日：2007-12-27

申请人： David Ihme ,  James C. Kemerling ,  William D. Cox

发明人： David Ihme ,  James C. Kemerling ,  William D. Cox

IPC分类号： H01L21/82

CPC分类号： H01G4/385 ,  H01L27/0805 ,  H01L2924/14 ,  H01L2924/00

摘要： A semiconductor device having a plurality of layers and a capacitor array that includes a plurality of individual capacitors. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections and capacitances of the plurality of individual capacitors in the capacitor array. The semiconductor device may include a metal structure disposed within the device to provide an electromagnetic shield for at least one of the plurality of individual capacitors in the capacitor array.

摘要翻译： 具有多个层的半导体器件和包括多个单独的电容器的电容器阵列。 半导体器件中的多个层中的至少一个可以是被配置为确定电容器阵列中的多个单独电容器的连接和电容的通孔层。 半导体器件可以包括设置在器件内的金属结构，以为电容器阵列中的多个独立电容器中的至少一个提供电磁屏蔽。

公开(公告)号：US06580289B2

公开(公告)日：2003-06-17

申请号：US10164455

申请日：2002-06-06

申请人： William D. Cox

发明人： William D. Cox

IPC分类号： H03K19177

CPC分类号： H03K19/17764 ,  G01R31/318321 ,  H03K19/1736 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17796

摘要： A semiconductor device and method of testing the device having a plurality of logic cells interconnected using vias to connect routing tracks that are disposed among a plurality of layers in the device. The logic cells in the device including at least two three-input look-up tables, one two-input look-up table and a flip-flop. The components in the logic cell are connected so that any look-up table can drive at least one input of any other look-up table and where the flip-flop is connected to the look-up tables so that any look-up table can drive an input of the flip-flop.

公开(公告)号：US07692309B2

公开(公告)日：2010-04-06

申请号：US11850791

申请日：2007-09-06

申请人： William D. Cox

发明人： William D. Cox

IPC分类号： H01L23/48

CPC分类号： H01L27/11898 ,  H01L27/0207 ,  H01L27/11803

摘要： An application-specific integrated circuit (ASIC) is customized using two non-adjacent via layers. An array of logic cells, each including a plurality of logic devices, are arranged in a plurality of non-customized base layers. A first routing grid, which includes a first non-customized metal routing layer, a customized via layer, and a second non-customized metal routing layer, is disposed on top of the plurality of non-customized layers. A second routing grid, which includes a third non-customized metal routing layer, another customized via layer, and a fourth non-customized metal routing layer, is disposed above the first routing grid. A non-customized via layer is disposed above the first routing grid and beneath the second routing grid. The routing grids and the non-customized via layer collectively facilitate routing connections to and from the logic cells.

摘要翻译： 专用集成电路（ASIC）使用两个不相邻的通孔层进行定制。 每个包括多个逻辑设备的逻辑单元阵列被布置在多个非定制的基础层中。 包括第一非定制金属路由层，定制通孔层和第二非定制金属路由层的第一路由网格被布置在多个非定制层的顶部上。 包括第三非定制金属路由层，另一个定制通路层和第四非定制金属路由层的第二路由网格设置在第一路由网格上方。 非定制通孔层设置在第一路由网格上方并位于第二路由网格之下。 路由网格和非定制的通过层共同促进与逻辑单元的路由连接。

公开(公告)号：US5552720A

公开(公告)日：1996-09-03

申请号：US349092

申请日：1994-12-01

申请人： Mukesh T. Lulla ,  William D. Cox

发明人： Mukesh T. Lulla ,  William D. Cox

IPC分类号： G06F17/50 ,  H01H37/76

CPC分类号： G06F17/5054

摘要： A sequence of antifuses to be programmed is determined by: determining whether a first antifuse of an unordered list of antifuses to be programmed could be programmed last without programming any antifuses which are not to be programmed, determining whether a second antifuse of the unordered list could be programmed last without programming any antifuses which are not be programmed, and determining whether the first and second antifuses could be programmed simultaneously without programming any antifuses which are not to be programmed. In this way, a programming set of antifuses which could be programmed simultaneously is determined. Once determined, the antifuses making up the programming set are added to the head of an ordered list and are removed from the unordered list. By repeatedly determining programming sets of antifuses and adding each successive set of antifuses to an ordered list of antifuses, an antifuse programming sequence is developed. An FPGA is programmed by simultaneously programming the antifuses in each programming set, the programming sets being programmed in the order they appear in the ordered list.

摘要翻译： 要编程的反熔丝序列通过以下方式来确定：确定是否可以最后编程要编程的反熔丝的无序列表的第一反熔丝，而不编程任何不被编程的反熔丝，确定无序列表的第二反熔丝是否可以 最后编程不编程任何不被编程的反熔丝，并且确定是否可以同时编程第一和第二反熔丝，而不编写任何不被编程的反熔丝。 以这种方式，确定可以同时编程的反熔丝的编程集合。 一旦确定，构成编程集的反熔丝将被添加到有序列表的头部，并从无序列表中移除。 通过重复地确定反熔丝的编程集合并将每个连续的反熔体组合加到有序的反熔丝列表中，开发了反熔丝编程序列。 通过在每个编程集合中同时编程反熔丝来编程FPGA，编程集按照它们在有序列表中出现的顺序进行编程。

公开(公告)号：US5544070A

公开(公告)日：1996-08-06

申请号：US937331

申请日：1992-08-27

申请人： William D. Cox ,  Andrew K. L. Chan ,  Richard J. Wong ,  James M. Apland ,  Kathryn E. Gordon

发明人： William D. Cox ,  Andrew K. L. Chan ,  Richard J. Wong ,  James M. Apland ,  Kathryn E. Gordon

IPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  H03K19/177

CPC分类号： H03K19/17764 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H03K19/17704 ,  H03K19/1778 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A programmable device comprises a first antifuse programmed with a first programming method and a second antifuse programmed with a second programming method, whereby an actual operating current flowing through the second antifuse exceeds a maximum permissible operating current of the first antifuse but does not exceed a maximum permissible operating current of the second antifuse, whereby an actual operating current flowing through the first antifuse does not exceed the maximum permissible operating current of the first antifuse, and whereby an actual operating current flowing through the second antifuse does not exceed the maximum permissible operating current of the second antifuse. By allowing the use of a programming method on some antifuses which would not be adequate for the programming of other antifuses, the realization of user-specific circuits in field programmable devices is facilitated and the reliability of user-specific circuits realized in field programmable devices is enhanced.

摘要翻译： 可编程器件包括用第一编程方法编程的第一反熔丝和用第二编程方法编程的第二反熔丝，由此流过第二反熔丝的实际工作电流超过第一反熔丝的最大允许工作电流但不超过最大值 第二反熔丝的允许工作电流，由此流过第一反熔丝的实际工作电流不超过第一反熔丝的最大允许工作电流，由此流过第二反熔丝的实际工作电流不超过最大允许工作电流 的第二个反熔丝。 通过允许在一些反熔丝上使用编程方法来编程其他抗反熔丝，对于现场可编程器件中的用户特定电路的实现是有利的，并且在现场可编程器件中实现的用户特定电路的可靠性是 增强。