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29 条记录 (耗时 0.016 秒)

    Power throttling method and apparatus
    1.
    发明申请
    Power throttling method and apparatus 失效
    功率节流方法和装置

    公开(公告)号：US20050044434A1

    公开(公告)日：2005-02-24

    申请号：US10645024

    申请日：2003-08-21

    申请人： James Kahle ,  David Shippy ,  Albert Norstrand

    发明人： James Kahle ,  David Shippy ,  Albert Norstrand

    IPC分类号： G06F1/32 ,  G06F1/26

    CPC分类号： G06F9/30112 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/30141 ,  G06F9/30189 ,  Y02D10/171 ,  Y02D50/20

    摘要： Disclosed is an apparatus which deactivates both the AC as well as the DC component of power for various functions in a CPU. The CPU partitions dataflow registers and arithmetic units such that voltage can be removed from the upper portion of dataflow registers when the software is not utilizing same. Clock signals are also prevented from being applied to these non-utilized components. As an example, if a 64 bit CPU (processor unit) is to be used with both 32 and 64 bit software, the mentioned components may be partitioned in equal sized upper and lower portions. The logic signal for activating the removal of voltage may be obtained from a software-accessible architected control register designated as a machine state register in some CPUs. The same logic may be used in connection with removing voltage and clocks from other specialized functional components such as the floating point unit when software instructions do not presently require same.

    摘要翻译： 公开了一种对CPU中的各种功能的AC以及DC分量进行停用的装置。 CPU分配数据流寄存器和算术单元，使得当软件不使用相同时，可以从数据流寄存器的上部去除电压。 还防止时钟信号被施加到这些未使用的组件。 作为示例，如果要使用32位和64位软件的64位CPU（处理器单元），则所提到的组件可以被分成相同大小的上部和下部。 用于激活电压去除的逻辑信号可以从在某些CPU中指定为机器状态寄存器的软件可访问的架构控制寄存器获得。 当软件指令当前不需要相同时，相同的逻辑可用于从其他专门功能组件（例如浮点单元）中去除电压和时钟。

    Software-controlled cache set management
    3.
    发明申请
    Software-controlled cache set management 失效
    软件控制缓存集管理

    公开(公告)号：US20050055507A1

    公开(公告)日：2005-03-10

    申请号：US10655367

    申请日：2003-09-04

    申请人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  James Kahle ,  David Shippy ,  Thuong Truong ,  Takeshi Yamazaki

    发明人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  James Kahle ,  David Shippy ,  Thuong Truong ,  Takeshi Yamazaki

    IPC分类号： G06F12/00 ,  G06F12/12

    CPC分类号： G06F12/126

    摘要： The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.

    摘要翻译： 本发明提供了根据替换管理表和最近最少使用的功能来选择性地覆盖高速缓存的集合。 根据地址未命中创建类标识符。 替换管理表可用于读取类标识符以创建标签替换控制标记。 包括多个集合的高速缓存可用于根据标签替换控制标记来禁用对多个集合中的至少一个的替换。

    Method and apparatus for coherent memory structure of heterogeneous processor systems
    4.
    发明申请
    Method and apparatus for coherent memory structure of heterogeneous processor systems 失效
    异构处理器系统的相干存储器结构的方法和装置

    公开(公告)号：US20050080998A1

    公开(公告)日：2005-04-14

    申请号：US10682386

    申请日：2003-10-09

    申请人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  James Kahle ,  David Shippy ,  Thuong Truong

    发明人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  James Kahle ,  David Shippy ,  Thuong Truong

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0835

    摘要： Disclosed is a coherent cache system that operates in conjunction with non-homogeneous processing units. A set of processing units of a first configuration has conventional cache and directly accesses common or shared system physical and virtual address memory through the use of a conventional MMU (Memory Management Unit). Additional processors of a different configuration and/or other devices that need to access system memory are configured to store accessed data in compatible caches. Each of the caches is compatible with a given protocol coherent memory management bus interspersed between the caches and the system memory.

    摘要翻译： 公开了与非均匀处理单元结合操作的一致的缓存系统。 一组第一配置的处理单元具有常规高速缓存，并且通过使用常规MMU（存储器管理单元）直接访问公用或共享系统物理和虚拟地址存储器。 需要访问系统存储器的不同配置和/或其他设备的其他处理器被配置为将访问的数据存储在兼容的高速缓存中。 每个缓存与散列在高速缓存和系统存储器之间的给定协议相干存储器管理总线兼容。

    Modular design method and apparatus
    6.
    发明申请
    Modular design method and apparatus 失效
    模块化设计方法和装置

    公开(公告)号：US20070052562A1

    公开(公告)日：2007-03-08

    申请号：US11191580

    申请日：2005-07-28

    申请人： Harm Hofstee ,  James Kahle ,  Takeshi Yamazaki

    发明人： Harm Hofstee ,  James Kahle ,  Takeshi Yamazaki

    IPC分类号： H03M7/40

    CPC分类号： G06F17/5045

    摘要： Disclosed is a procedure or design approach for functional modules that may be used in connection with a multiprocessor integrated circuit chip. The approach includes keeping the dimensions of each module substantially the same and having the bus, power, clock and I/O connection configured the same on all modules. Further requirements for ease of use are to generalize the capability of each module as much as possible and to decentralize functions such as testing to be primarily performed within each module. The use of such considerations or rules substantially eases the design of a given type of custom chips, and based upon an initial chip design greatly facilitates the design of further custom chips, similar in application, but subsequent to the successful completion of the initial chip. The standardization modules and replication of the modules on a given chip also reduces physical verification time in initial chip design as well as redesign time of the initial chip when requirements for chip capability are redefined or otherwise changed. Any subsequent or further custom chips can include more or less of specific modules based upon already established parameters.

    摘要翻译： 公开了可以与多处理器集成电路芯片结合使用的功能模块的过程或设计方法。 该方法包括保持每个模块的尺寸基本相同，并使总线，电源，时钟和I / O连接在所有模块上配置相同。 对易用性的进一步要求是尽可能地推广每个模块的能力，并将诸如测试之类的功能分散在每个模块内主要执行。 这种考虑或规则的使用大大简化了给定类型的定制芯片的设计，并且基于初始的芯片设计极大地促进了其他定制芯片的设计，其应用类似，但是在初始芯片的成功完成之后。 给定芯片上的标准化模块和模块的复制也减少了初始芯片设计中的物理验证时间，以及在重新定义或改变芯片能力要求时初始芯片的重新设计时间。 任何后续或进一步的定制芯片可以基于已经建立的参数包括或多或少的特定模块。

    SIMD-RISC microprocessor architecture
    8.
    发明申请
    SIMD-RISC microprocessor architecture 失效
    SIMD-RISC微处理器架构

    公开(公告)号：US20050160097A1

    公开(公告)日：2005-07-21

    申请号：US11065707

    申请日：2005-02-24

    申请人： Michael Gschwind ,  Harm Hofstee ,  Martin Hopkins ,  James Kahle

    发明人： Michael Gschwind ,  Harm Hofstee ,  Martin Hopkins ,  James Kahle

    IPC分类号： G06F15/16 ,  G06F9/44 ,  G06F9/50 ,  G06F15/177 ,  G06F15/80 ,  H04L29/06 ,  H04L29/08 ,  G06F17/30

    CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

    摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

    摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。

    Multi-chip module with third dimension interconnect
    9.
    发明申请
    Multi-chip module with third dimension interconnect 审中-公开
    具有三维互连的多芯片模块

    公开(公告)号：US20050138325A1

    公开(公告)日：2005-06-23

    申请号：US11050038

    申请日：2005-02-03

    申请人： Harm Hofstee ,  Charles Johns ,  James Kahle

    发明人： Harm Hofstee ,  Charles Johns ,  James Kahle

    IPC分类号： G06F15/16 ,  G06F9/44 ,  G06F9/50 ,  G06F15/177 ,  G06F15/80 ,  H04L29/06 ,  H04L29/08 ,  G06F15/00 ,  G06F15/173

    CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

    摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

    摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。

    System and Method for Sharing Memory by Heterogeneous Processors
    10.
    发明申请
    System and Method for Sharing Memory by Heterogeneous Processors 有权
    异构处理器共享内存的系统和方法

    公开(公告)号：US20070283103A1

    公开(公告)日：2007-12-06

    申请号：US11840284

    申请日：2007-08-17

    申请人： Harm Hofstee ,  Charles Johns ,  James Kahle

    发明人： Harm Hofstee ,  Charles Johns ,  James Kahle

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0284 ,  G06F13/1652

    摘要： A system for sharing memory by heterogeneous processors, each of which is adapted to process its own instruction set, is presented. A common bus is used to couple the common memory to the various processors. In one embodiment, a cache for more than one of the processors is stored in the shared memory. In another embodiment, some of the processors include a local memory area that is mapped to the shared memory pool. In yet another embodiment, local memory included on one or more of the processors is partially shared so that some of the local memory is mapped to the shared memory area, while remaining memory in the local memory is private to the particular processor.

    摘要翻译： 提出了一种用于通过异构处理器共享存储器的系统，每个处理器适于处理其自己的指令集。 公共总线用于将公共存储器耦合到各种处理器。 在一个实施例中，用于多于一个处理器的高速缓存存储在共享存储器中。 在另一个实施例中，一些处理器包括映射到共享存储器池的本地存储器区域。 在另一个实施例中，包括在一个或多个处理器中的本地存储器被部分地共享，使得一些本地存储器被映射到共享存储器区域，而本地存储器中的剩余存储器对于特定处理器是专用的。