摘要:
Provided are a method, system, and article of manufacture for error checking addressable blocks in storage. Addressable blocks of data are stored in a storage in stripes, wherein each stripe includes a plurality of data blocks for one of the addressable blocks and at least one checksum block including checksum data derived from the data blocks for the addressable block. A write request is received to modify data in one of the addressable blocks. The write and updating the checksum are performed in the stripe having the modified addressable block. An indication is made to perform an error checking operation on the stripe for the modified addressable block in response to the write request, wherein the error checking operation reads the data blocks and the checksum in the stripe to determine if the checksum data is accurate. An error handling operation is initiated in response to determining that the checksum data is not accurate.
摘要:
Provided are a method, system, and article of manufacture for error checking addressable blocks in storage. Addressable blocks of data are stored in a storage in stripes, wherein each stripe includes a plurality of data blocks for one of the addressable blocks and at least one checksum block including checksum data derived from the data blocks for the addressable block. A write request is received to modify data in one of the addressable blocks. The write and updating the checksum are performed in the stripe having the modified addressable block. An indication is made to perform an error checking operation on the stripe for the modified addressable block in response to the write request, wherein the error checking operation reads the data blocks and the checksum in the stripe to determine if the checksum data is accurate. An error handling operation is initiated in response to determining that the checksum data is not accurate.
摘要:
A set of disks in a plurality of disk arrays are configured to have one or more spare partitions. Upon detecting a faulty disk in a faulty array, the method involves the steps of: (a) migrating data in the faulty array containing the faulty disk to one or more spare partitions; (b) reconfiguring the faulty array to form a new array without the faulty disk; (c) migrating data from one or more spare partitions in the set of disks to the reconfigured new array; (d) monitoring to identify when overall spare capacity falls below a predetermined threshold; and when the predetermined threshold is exceeded, scheduling a service visit for replacement of the failed disks.
摘要:
A system (and method) for determining reconstruction formulas for partial strip reconstruction in a storage system in which a plurality of lost strips have been detected, includes using a combination of a direct reconstruction method and a sequential reconstruction method.
摘要:
A system (and method) for determining reconstruction formulas for partial strip reconstruction in a storage system in which a plurality of lost strips have been detected, includes using a combination of a direct reconstruction method and a sequential reconstruction method.
摘要:
A set of disks in a plurality of disk arrays are configured to have one or more spare partitions. Upon detecting a faulty disk in a faulty array, the method involves the steps of: (a) migrating data in the faulty array containing the faulty disk to one or more spare partitions; (b) reconfiguring the faulty array to form a new array without the faulty disk; (c) migrating data from one or more spare partitions in the set of disks to the reconfigured new array; (d) monitoring to identify when overall spare capacity falls below a predetermined threshold; and when the predetermined threshold is exceeded, scheduling a service visit for replacement of the failed disks.
摘要:
Embodiments of the invention enable a storage cache, comprising flash memory devices, to have direct block access to the flash such that the physical block addresses are presented to the storage system's cache layer, which thereby controls the storage cache data stream. An aspect of the invention includes a caching storage system. The caching storage system comprises a plurality of flash memory units organized in an array configuration. Each of the plurality of flash memory units includes at least one flash memory device and a flash unit controller. Each flash unit controller provides the caching storage system with direct physical block access to its corresponding at least one flash memory device. The caching storage system further comprises a storage cache controller. The storage cache controller selects physical block address locations (within a flash memory device) to be erased where data are to be written, issues erase commands to a flash unit controller corresponding to the selected physical block address locations, and issues page write operations to a set of erase blocks.
摘要:
Structure, method, and computer program for an explicitly tunable device controller. Method supports high-performance I/O without imposing additional overhead during normal input/output operations. Tuning is performed during explicit pre-I/O operation phase. In one embodiment, invention provides a method for tuning device controller operating characteristics to suit attributes of a data stream in which the method comprises: monitoring a data stream and collecting attributes of the monitored data stream; generating performance metrics of the data stream based on the collected attributes and a plurality of different assumed device controller configurations; comparing expected performance of the plurality of different device controller configurations for effectiveness with a future data stream having similar data stream type attributes to the monitored data stream; and selecting device controller characteristics to provide an effective match between the data stream type and the device controller configuration. In one embodiment, the controller configuration is adjusted automatically and dynamically during normal I/O operations to suit the particular input/output operation encountered. Configuration information may be selected for example, from such parameters as data redundancy level, RAID level, number of drives in a RAID array, memory module size, cache line size, direct I/O or cached I/O mode, read-ahead cache enable or read-ahead cache disable, cache line aging, cache size, or combinations thereof. A storage device controller, such as a RAID controller, implementing the inventive method in computer program software or firmware is also provided as are computer system having a host computer coupled to a storage system through the inventive controller.
摘要:
Embodiments of the invention enable a storage cache, comprising flash memory devices, to have direct block access to the flash such that the physical block addresses are presented to the storage system's cache layer, which thereby controls the storage cache data stream. An aspect of the invention includes a caching storage system. The caching storage system comprises a plurality of flash memory units organized in an array configuration. Each of the plurality of flash memory units includes at least one flash memory device and a flash unit controller. Each flash unit controller provides the caching storage system with direct physical block access to its corresponding at least one flash memory device. The caching storage system further comprises a storage cache controller. The storage cache controller selects physical block address locations (within a flash memory device) to be erased where data are to be written, issues erase commands to a flash unit controller corresponding to the selected physical block address locations, and issues page write operations to a set of erase blocks.
摘要:
The present invention describes a method and system for interfacing a plurality of device controllers to an array of data storage devices by serial connection. The device controllers are coupled to a serial interface by a bus and the devices of the storage array are coupled to the serial interface by a serial connection. The serial interface receives controller signals through the bus and multiplexes the signals onto the serial connections of the storage array. Arbitration between the various device controllers seeking access to the storage array is resolved through bus protocol and through drive based reserve/release registers in the serial interface processor.