-
1.发明授权公开(公告)号：US08737028B2
公开(公告)日：2014-05-27
申请号：US13312047
申请日：2011-12-06
CPC分类号： H02H9/046
摘要： Methods for responding to an electrostatic discharge (ESD) event on a voltage rail, ESD protection circuits, and design structures for an ESD protection circuit. An RC network of the ESD protection circuit includes a capacitor coupled to a field effect transistor at a node. The node of the RC network is coupled with an input of the inverter. The field-effect transistor is coupled with an output of the inverter. In response to an ESD event, a trigger signal is supplied from the RC network to the input of the inverter, which drives a clamp device to discharge current from the ESD event from the voltage rail. An RC time constant of the RC network is increased in response to the ESD event to sustain the discharge of the current by the clamp device.
摘要翻译： 用于响应电压轨上的静电放电（ESD）事件，ESD保护电路以及ESD保护电路的设计结构的方法。 ESD保护电路的RC网络包括耦合到节点处的场效应晶体管的电容器。 RC网络的节点与逆变器的输入端相连。 场效应晶体管与反相器的输出端相连。 响应于ESD事件，触发信号从RC网络提供给逆变器的输入，该驱动器驱动钳位装置以从ESD电压放电来自电压轨。 响应于ESD事件，RC网络的RC时间常数增加以维持钳位装置的电流放电。
-
2.发明申请公开(公告)号：US20130141823A1
公开(公告)日：2013-06-06
申请号：US13312047
申请日：2011-12-06
CPC分类号： H02H9/046
摘要： Methods for responding to an electrostatic discharge (ESD) event on a voltage rail, ESD protection circuits, and design structures for an ESD protection circuit. An RC network of the ESD protection circuit includes a capacitor coupled to a field effect transistor at a node. The node of the RC network is coupled with an input of the inverter. The field-effect transistor is coupled with an output of the inverter. In response to an ESD event, a trigger signal is supplied from the RC network to the input of the inverter, which drives a clamp device to discharge current from the ESD event from the voltage rail. An RC time constant of the RC network is increased in response to the ESD event to sustain the discharge of the current by the clamp device.
摘要翻译： 用于响应电压轨上的静电放电（ESD）事件，ESD保护电路以及ESD保护电路的设计结构的方法。 ESD保护电路的RC网络包括耦合到节点处的场效应晶体管的电容器。 RC网络的节点与逆变器的输入端相连。 场效应晶体管与反相器的输出端相连。 响应于ESD事件，触发信号从RC网络提供给逆变器的输入，该驱动器驱动钳位装置以从ESD电压放电来自电压轨。 响应于ESD事件，RC网络的RC时间常数增加以维持钳位装置的电流放电。
-
公开(公告)号：US08610249B2
公开(公告)日：2013-12-17
申请号：US13434964
申请日：2012-03-30
申请人： James P. Di Sarro , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： James P. Di Sarro , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H01L21/02
CPC分类号： H01L27/0805 , H01L21/845 , H01L27/1211 , H01L28/90 , H01L29/94
摘要： Disclosed herein are embodiments of non-planar capacitor. The non-planar capacitor can comprise a plurality of fins above a semiconductor substrate. Each fin can comprise at least an insulator section on the semiconductor substrate and a semiconductor section, which has essentially uniform conductivity, stacked above the insulator section. A gate structure can traverse the center portions of the fins. This gate structure can comprise a conformal dielectric layer and a conductor layer (e.g., a blanket or conformal conductor layer) on the dielectric layer. Such a non-planar capacitor can exhibit a first capacitance, which is optionally tunable, between the conductor layer and the fins and a second capacitance between the conductor layer and the semiconductor substrate. Also disclosed herein are method embodiments, which can be used to form such a non-planar capacitor and which are compatible with current state of the art multi-gate non-planar field effect transistor (MUGFET) processing.
摘要翻译： 这里公开了非平面电容器的实施例。 非平面电容器可以包括在半导体衬底上方的多个鳍片。 每个翅片可以包括半导体衬底上的至少绝缘体部分和在绝缘体部分上方堆叠具有基本上均匀的导电性的半导体部分。 门结构可以穿过翅片的中心部分。 该栅极结构可以包括在电介质层上的共形介电层和导体层（例如，覆盖层或保形导体层）。 这种非平面电容器可以在导体层和散热片之间展现可选地可调谐的第一电容和导体层与半导体衬底之间的第二电容。 本文还公开了可用于形成这种非平面电容器并且与现有技术的多栅极非平面场效应晶体管（MUGFET）处理兼容的方法实施例。
-
公开(公告)号：US20130256835A1
公开(公告)日：2013-10-03
申请号：US13434964
申请日：2012-03-30
申请人： James P. Di Sarro , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： James P. Di Sarro , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
CPC分类号： H01L27/0805 , H01L21/845 , H01L27/1211 , H01L28/90 , H01L29/94
摘要： Disclosed herein are embodiments of non-planar capacitor. The non-planar capacitor can comprise a plurality of fins above a semiconductor substrate. Each fin can comprise at least an insulator section on the semiconductor substrate and a semiconductor section, which has essentially uniform conductivity, stacked above the insulator section. A gate structure can traverse the center portions of the fins. This gate structure can comprise a conformal dielectric layer and a conductor layer (e.g., a blanket or conformal conductor layer) on the dielectric layer. Such a non-planar capacitor can exhibit a first capacitance, which is optionally tunable, between the conductor layer and the fins and a second capacitance between the conductor layer and the semiconductor substrate. Also disclosed herein are method embodiments, which can be used to form such a non-planar capacitor and which are compatible with current state of the art multi-gate non-planar field effect transistor (MUGFET) processing.
摘要翻译： 这里公开了非平面电容器的实施例。 非平面电容器可以包括在半导体衬底上方的多个鳍片。 每个翅片可以包括半导体衬底上的至少绝缘体部分和在绝缘体部分上方堆叠具有基本上均匀的导电性的半导体部分。 门结构可以穿过翅片的中心部分。 该栅极结构可以包括在电介质层上的共形介电层和导体层（例如，覆盖层或保形导体层）。 这种非平面电容器可以在导体层和散热片之间展现可选地可调谐的第一电容和导体层与半导体衬底之间的第二电容。 本文还公开了可用于形成这种非平面电容器并且与现有技术的多栅极非平面场效应晶体管（MUGFET）处理兼容的方法实施例。
-
公开(公告)号：US08634174B2
公开(公告)日：2014-01-21
申请号：US13115492
申请日：2011-05-25
申请人： Michel J. Abou-Khalil , James P. Di Sarro , Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Yang Yang
发明人： Michel J. Abou-Khalil , James P. Di Sarro , Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Yang Yang
CPC分类号： H02H9/046 , G06F17/5063 , H01L27/0285
摘要： Protection circuits, design structures, and methods for isolating the gate and gate dielectric of a field-effect transistor from electrostatic discharge (ESD). A protection field-effect transistor is located between a protected field-effect transistor and a voltage rail. Under normal operating conditions, the protection field-effect transistor is saturated so that the protected field-effect transistor is coupled to the voltage rail. The protection field-effect transistor may be driven into a cutoff condition in response to an ESD event while the chip is unpowered, which increases the series resistance of an ESD current path between the gate of the protected field-effect transistor and the voltage rail. The voltage drop across the protection field-effect transistor may reduce the ESD stress on the gate dielectric of the protected field-effect transistor. Alternatively, the gate and source of an existing field-effect transistor are selectively coupled provide ESD isolation to the protected field-effect transistor.
摘要翻译： 用于将场效应晶体管的栅极和栅极电介质与静电放电（ESD）隔离的保护电路，设计结构和方法。 保护场效应晶体管位于受保护的场效应晶体管和电压轨之间。 在正常工作条件下，保护场效应晶体管饱和，使受保护的场效应晶体管耦合到电压轨。 保护场效应晶体管可以在芯片无电源时响应于ESD事件而被驱动成截止状态，这增加了受保护的场效应晶体管的栅极与电压轨之间的ESD电流路径的串联电阻。 保护场效应晶体管两端的电压降可以降低受保护的场效应晶体管的栅极电介质上的ESD应力。 或者，现有的场效应晶体管的栅极和源极被选择性地耦合到提供ESD隔离到受保护的场效应晶体管。
-
公开(公告)号：US20120300349A1
公开(公告)日：2012-11-29
申请号：US13115492
申请日：2011-05-25
申请人： Michel J. Abou-Khalil , James P. Di Sarro , Robert J. Gauthier, JR. , Junjun Li , Souvick Mitra , Yang Yang
发明人： Michel J. Abou-Khalil , James P. Di Sarro , Robert J. Gauthier, JR. , Junjun Li , Souvick Mitra , Yang Yang
CPC分类号： H02H9/046 , G06F17/5063 , H01L27/0285
摘要： Protection circuits, design structures, and methods for isolating the gate and gate dielectric of a field-effect transistor from electrostatic discharge (ESD). A protection field-effect transistor is located between a protected field-effect transistor and a voltage rail. Under normal operating conditions, the protection field-effect transistor is saturated so that the protected field-effect transistor is coupled to the voltage rail. The protection field-effect transistor may be driven into a cutoff condition in response to an ESD event while the chip is unpowered, which increases the series resistance of an ESD current path between the gate of the protected field-effect transistor and the voltage rail. The voltage drop across the protection field-effect transistor may reduce the ESD stress on the gate dielectric of the protected field-effect transistor. Alternatively, the gate and source of an existing field-effect transistor are selectively coupled provide ESD isolation to the protected field-effect transistor.
摘要翻译： 用于将场效应晶体管的栅极和栅极电介质与静电放电（ESD）隔离的保护电路，设计结构和方法。 保护场效应晶体管位于受保护的场效应晶体管和电压轨之间。 在正常工作条件下，保护场效应晶体管饱和，使受保护的场效应晶体管耦合到电压轨。 保护场效应晶体管可以在芯片无电源时响应于ESD事件而被驱动成截止状态，这增加了受保护的场效应晶体管的栅极与电压轨之间的ESD电流路径的串联电阻。 保护场效应晶体管两端的电压降可以降低受保护的场效应晶体管的栅极电介质上的ESD应力。 或者，现有的场效应晶体管的栅极和源极被选择性地耦合到提供ESD隔离到受保护的场效应晶体管。
-
7.发明授权Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers 有权用于动态偏置的结构和方法，以改善电流模式逻辑（CML）驱动器的ESD稳健性公开(公告)号：US09219055B2
公开(公告)日：2015-12-22
申请号：US13517849
申请日：2012-06-14
IPC分类号： H03K19/086 , H03K19/0175 , H01L27/02
CPC分类号： H02H9/005 , G06F17/5081 , H01L27/0251 , H01L27/0281 , H01L27/0285 , H02H9/04 , H02H9/046 , H03K17/687
摘要： An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.
摘要翻译： 具有CML驱动器的集成电路，其包括驱动器偏置网络。 第一输出焊盘和第二输出焊盘连接到电压焊盘。 第一驱动器连接到第一输出焊盘和电压焊盘。 第二驱动器连接到第二输出焊盘和电压焊盘。 第一ESD电路连接到电压焊盘，第一输出焊盘和第一驱动器。 第二ESD电路连接到电压焊盘，第二输出焊盘和第二驱动器。 当在第一输出焊盘处发生ESD事件时，第一ESD电路将第一驱动器偏压到电压焊盘的电压，并且当在第二ESD处发生ESD事件时，第二ESD电路将第二驱动器偏压到电压焊盘的电压 输出板。
-
公开(公告)号：US20130335099A1
公开(公告)日：2013-12-19
申请号：US13517849
申请日：2012-06-14
CPC分类号： H02H9/005 , G06F17/5081 , H01L27/0251 , H01L27/0281 , H01L27/0285 , H02H9/04 , H02H9/046 , H03K17/687
摘要： An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.
-
公开(公告)号：US08680573B2
公开(公告)日：2014-03-25
申请号：US13455653
申请日：2012-04-25
IPC分类号： H01L29/66
CPC分类号： H01L21/8222 , H01L21/84 , H01L27/0262 , H01L27/1203
摘要： Device structures, design structures, and fabrication methods for a silicon controlled rectifier. A well of a first conductivity type is formed in a device region, which may be defined from a device layer of a semiconductor-on-insulator substrate. A doped region of a second conductivity type is formed in the well. A cathode of a silicon controlled rectifier and a cathode of a diode are formed in the device region. The silicon controlled rectifier comprises a first portion of the well and an anode comprised of a first portion of the doped region. The diode comprises a second portion of the well and an anode comprised of a second portion of the doped region.
摘要翻译： 可控硅整流器的器件结构，设计结构和制造方法。 第一导电类型的阱形成在器件区域中，其可以由绝缘体上半导体衬底的器件层限定。 在井中形成第二导电类型的掺杂区域。 在器件区域中形成可控硅整流器的阴极和二极管的阴极。 可控硅整流器包括阱的第一部分和由掺杂区域的第一部分组成的阳极。 二极管包括阱的第二部分和由掺杂区域的第二部分组成的阳极。
-
公开(公告)号：US08987073B2
公开(公告)日：2015-03-24
申请号：US13546509
申请日：2012-07-11
CPC分类号： H01L23/60 , H01L21/84 , H01L27/0251 , H01L27/1203 , H01L29/66545 , H01L29/66636 , H01L29/7841 , H01L2924/0002 , H01L2924/00
摘要： Device structures, design structures, and fabrication methods for a metal-oxide-semiconductor field-effect transistor. A gate structure is formed on a top surface of a substrate. First and second trenches are formed in the substrate adjacent to a sidewall of the gate structure. The second trench is formed laterally between the first trench and the first sidewall. First and second epitaxial layers are respectively formed in the first and second trenches. A contact is formed to the first epitaxial layer, which serves as a drain. The second epitaxial layer in the second trench is not contacted so that the second epitaxial layer serves as a ballasting resistor.
摘要翻译： 金属氧化物半导体场效应晶体管的器件结构，设计结构和制造方法。 栅极结构形成在衬底的顶表面上。 第一和第二沟槽形成在与栅极结构的侧壁相邻的衬底中。 第二沟槽横向形成在第一沟槽和第一侧壁之间。 第一和第二外延层分别形成在第一和第二沟槽中。 形成到作为漏极的第一外延层的接触。 第二沟槽中的第二外延层不接触，使得第二外延层用作镇流电阻器。
-
-
-
-
-
-
-
-
-
搜索结果
12 条记录 (耗时 0.025 秒)