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1.发明授权公开(公告)号：US08429367B2
公开(公告)日：2013-04-23
申请号：US11965953
申请日：2007-12-28
申请人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner , Gopikrishna Jandhyala
发明人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner , Gopikrishna Jandhyala
IPC分类号： G06F1/04
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict whether a scheduled request will be issued to a rank. The memory controller may also include logic to predict whether a scheduled request will not be issued to the rank. In some embodiments, the clock enable (CKE) is asserted or de-asserted to a rank based, at least in part, on the predictions. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于时钟使能（CKE）协调的系统，方法和装置。 在一些实施例中，存储器控制器包括用于预测排定的请求是否将被发布到等级的逻辑。 存储器控制器还可以包括用于预测排定的请求是否将不被发布到等级的逻辑。 在一些实施例中，时钟使能（CKE）至少部分地基于预测被断言或取消断言为等级。 描述和要求保护其他实施例。
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2.发明申请公开(公告)号：US20090172681A1
公开(公告)日：2009-07-02
申请号：US11965953
申请日：2007-12-28
申请人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner , Gopikrishna Jandhyala
发明人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner , Gopikrishna Jandhyala
IPC分类号： G06F9/46
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict whether a scheduled request will be issued to a rank. The memory controller may also include logic to predict whether a scheduled request will not be issued to the rank. In some embodiments, the clock enable (CKE) is asserted or de-asserted to a rank based, at least in part, on the predictions. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于时钟使能（CKE）协调的系统，方法和装置。 在一些实施例中，存储器控制器包括用于预测排定的请求是否将被发布到等级的逻辑。 存储器控制器还可以包括用于预测排定的请求是否将不被发布到等级的逻辑。 在一些实施例中，时钟使能（CKE）至少部分地基于预测被断言或取消断言为等级。 描述和要求保护其他实施例。
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公开(公告)号：US20090171875A1
公开(公告)日：2009-07-02
申请号：US11965955
申请日：2007-12-28
申请人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner
发明人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner
IPC分类号： G06N5/02
CPC分类号： G06N5/02
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for rank coordination. In some embodiments, a host includes rank coordination logic. The rank coordination logic may include performance measurement logic to measure a performance of a memory channel and dwell period control logic to select a length of a dwell period based, at least in part, on the performance of the memory channel. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于秩协调的系统，方法和装置。 在一些实施例中，主机包括秩协调逻辑。 秩协调逻辑可以包括性能测量逻辑，以至少部分地基于存储器通道的性能来测量存储器通道的性能和停留周期控制逻辑以选择驻留时间的长度。 描述和要求保护其他实施例。
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公开(公告)号：US07885914B2
公开(公告)日：2011-02-08
申请号：US11965955
申请日：2007-12-28
申请人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner
发明人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner
IPC分类号： G06N5/02
CPC分类号： G06N5/02
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for rank coordination. In some embodiments, a host includes rank coordination logic. The rank coordination logic may include performance measurement logic to measure a performance of a memory channel and dwell period control logic to select a length of a dwell period based, at least in part, on the performance of the memory channel. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于秩协调的系统，方法和装置。 在一些实施例中，主机包括秩协调逻辑。 秩协调逻辑可以包括性能测量逻辑，以至少部分地基于存储器通道的性能来测量存储器通道的性能和停留周期控制逻辑以选择驻留时间的长度。 描述和要求保护其他实施例。
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公开(公告)号：US20090172442A1
公开(公告)日：2009-07-02
申请号：US11968142
申请日：2007-12-31
IPC分类号： G06F1/00
CPC分类号： G06F1/26 , G06F1/3225
摘要： Embodiments of the invention supply power to DRAM or other memory devices with a multi-phase voltage regulator. A power controller coupled to the multi-phase voltage regulator causes one or more phases of the multi-phase voltage regulator to be activated or deactivated (shed) according to predetermined criteria. Embodiments of the invention thus improve power management by providing one or more reduced power states for the memory devices. Other embodiments are described.
摘要翻译： 本发明的实施例用多相电压调节器向DRAM或其他存储器件供电。 耦合到多相电压调节器的功率控制器根据预定标准使多相电压调节器的一个或多个相位被激活或去激活（脱落）。 因此，本发明的实施例通过为存储器件提供一个或多个降低的功率状态来改善功率管理。 描述其他实施例。
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公开(公告)号：US07804733B2
公开(公告)日：2010-09-28
申请号：US11968142
申请日：2007-12-31
IPC分类号： G11C7/00
CPC分类号： G06F1/26 , G06F1/3225
摘要： Embodiments of the invention supply power to DRAM or other memory devices with a multi-phase voltage regulator. A power controller coupled to the multi-phase voltage regulator causes one or more phases of the multi-phase voltage regulator to be activated or deactivated (shed) according to predetermined criteria. Embodiments of the invention thus improve power management by providing one or more reduced power states for the memory devices. Other embodiments are described.
摘要翻译： 本发明的实施例用多相电压调节器向DRAM或其他存储器件供电。 耦合到多相电压调节器的功率控制器根据预定标准使多相电压调节器的一个或多个相位被激活或去激活（脱落）。 因此，本发明的实施例通过为存储器件提供一个或多个降低的功率状态来改善功率管理。 描述其他实施例。
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7.发明授权公开(公告)号：US08719606B2
公开(公告)日：2014-05-06
申请号：US12059994
申请日：2008-03-31
申请人： Son H. Lam , James W. Alexander
发明人： Son H. Lam , James W. Alexander
CPC分类号： G11C7/02 , G11C5/144 , G11C7/1045 , G11C7/1066 , G11C7/22
摘要： Methods and apparatus relating to optimization of performance and/or power consumption during memory power down state are described. In an embodiment, a memory controller may include logic to cause one or more ranks of a DIMM to enter a clock enable slow mode. Other embodiments are also described.
摘要翻译： 描述与存储器掉电状态期间性能和/或功耗优化有关的方法和装置。 在一个实施例中，存储器控制器可以包括使DIMM的一个或多个等级进入时钟使能慢速模式的逻辑。 还描述了其它实施例。
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8.发明申请公开(公告)号：US20090249097A1
公开(公告)日：2009-10-01
申请号：US12059994
申请日：2008-03-31
申请人： Son H. Lam , James W. Alexander
发明人： Son H. Lam , James W. Alexander
IPC分类号： G06F1/00
CPC分类号： G11C7/02 , G11C5/144 , G11C7/1045 , G11C7/1066 , G11C7/22
摘要： Methods and apparatus relating to optimization of performance and/or power consumption during memory power down state are described. In an embodiment, a memory controller may include logic to cause one or more ranks of a DIMM to enter a clock enable slow mode. Other embodiments are also described.
摘要翻译： 描述与存储器掉电状态期间性能和/或功耗优化有关的方法和装置。 在一个实施例中，存储器控制器可以包括使DIMM的一个或多个等级进入时钟使能慢速模式的逻辑。 还描述了其它实施例。
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9.发明申请SUPPLY VOLTAGE CONTROL BASED AT LEAST IN PART ON POWER STATE OF INTEGRATED CIRCUIT 审中-公开基于集成电路功率状态的供电电压控制公开(公告)号：US20150109051A1
公开(公告)日：2015-04-23
申请号：US14582799
申请日：2014-12-24
摘要： Disclosed is a switching voltage regulator circuitry controlled to supply a voltage to at least a portion of an integrated circuit (IC). Information corresponding to a current load for a different power state of at least a portion of the IC is received. The switching voltage regulator circuitry is controlled to adjust the voltage to a different value based at least in part on the received information. Disclosed is a voltage received for a power state of at least a portion of an IC having first logic to perform one or more functions and second logic integrated with the first logic. Information corresponding to a current load for a different power state of at least a portion of the IC is sent from the second logic to voltage regulator control logic to adjust the voltage to a different value.
摘要翻译： 公开了一种被控制为向集成电路（IC）的至少一部分提供电压的开关稳压器电路。 接收对应于IC的至少一部分的不同功率状态的当前负载的信息。 控制开关电压调节器电路以至少部分地基于所接收的信息将电压调整到不同的值。 公开了针对具有执行一个或多个功能的第一逻辑的IC的至少一部分的功率状态接收的电压和与第一逻辑集成的第二逻辑。 对应于IC的至少一部分的不同功率状态的当前负载的信息从第二逻辑被发送到电压调节器控制逻辑以将电压调整到不同的值。
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公开(公告)号：US08482269B2
公开(公告)日：2013-07-09
申请号：US13299331
申请日：2011-11-17
IPC分类号： G05F1/40
摘要： Disclosed is a switching voltage regulator circuitry controlled to supply a voltage to at least a portion of an integrated circuit (IC). Information corresponding to a current load for a different power state of at least a portion of the IC is received. The switching voltage regulator circuitry is controlled to adjust the voltage to a different value based at least in part on the received information. Disclosed is a voltage received for a power state of at least a portion of an IC having first logic to perform one or more functions and second logic integrated with the first logic. Information corresponding to a current load for a different power state of at least a portion of the IC is sent from the second logic to voltage regulator control logic to adjust the voltage to a different value.
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