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136 条记录 (耗时 0.026 秒)

    Method and apparatus for bus repeater tapering
    1.
    发明授权
    Method and apparatus for bus repeater tapering 有权
    总线中继器渐变的方法和装置

    公开(公告)号：US07684520B2

    公开(公告)日：2010-03-23

    申请号：US10334746

    申请日：2002-12-31

    申请人： James W. Tschanz ,  Muhammad M. Khellah ,  Yibin Ye ,  Vivek K. De

    发明人： James W. Tschanz ,  Muhammad M. Khellah ,  Yibin Ye ,  Vivek K. De

    IPC分类号： H04L27/00

    CPC分类号： H04L25/242

    摘要： A method and apparatus for bus repeater tapering. The sizing of repeaters on a portion of one transmission line is chosen to propagate a signal transition at a particular rate. The sizing of repeaters on a substantially parallel portion of another transmission line, is chosen to propagate a second signal transition at a different rate. Thus, the worst-case capacitance coupling factor between the two transmission lines may be reduced.

    摘要翻译： 一种用于总线中继器锥形化的方法和装置。 选择一个传输线路的一部分上的中继器的大小以传播特定速率的信号转换。 选择在另一传输线的基本平行部分上的中继器的尺寸以便以不同的速率传播第二信号转换。 因此，可以减小两条传输线之间的最坏情况电容耦合系数。

    SRAM device having forward body bias control
    2.
    发明授权
    SRAM device having forward body bias control 有权
    具有前向偏置控制的SRAM器件

    公开(公告)号：US07423899B2

    公开(公告)日：2008-09-09

    申请号：US10812894

    申请日：2004-03-31

    申请人： Stephen H. Tang ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek K. De ,  James W. Tschanz

    发明人： Stephen H. Tang ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek K. De ,  James W. Tschanz

    IPC分类号： G11C11/00 ,  G11C5/14

    CPC分类号： G11C11/412

    摘要： A SRAM device is provided having a plurality of memory cells. Each memory cell may include a plurality of transistors coupled in a cross-coupled inverter configuration. An NMOS transistor may be coupled to a body of the two PMOS transistors in the cross-coupled inverter configuration so as to apply a forward body bias to the PMOS transistors of the cross-coupled inverter configuration. A power control unit may control a supply voltage to each of the PMOS transistors as well as apply the switching signal to the NMOS transistor based on a STANDBY mode of the memory cell.

    摘要翻译： 提供具有多个存储单元的SRAM器件。 每个存储单元可以包括以交叉耦合的反相器配置耦合的多个晶体管。 NMOS晶体管可以以交叉耦合的反相器配置耦合到两个PMOS晶体管的主体，以便向交叉耦合的反相器配置的PMOS晶体管施加正向偏置。 功率控制单元可以控制每个PMOS晶体管的电源电压，并且基于存储器单元的STANDBY模式将开关信号施加到NMOS晶体管。

    Skewed repeater bus
    6.
    发明授权
    Skewed repeater bus 失效

    公开(公告)号：US06784688B2

    公开(公告)日：2004-08-31

    申请号：US10334410

    申请日：2002-12-30

    申请人： Muhammad M. Khellah ,  James W. Tschanz ,  Yibin Ye ,  Vivek K. De

    发明人： Muhammad M. Khellah ,  James W. Tschanz ,  Yibin Ye ,  Vivek K. De

    IPC分类号： H03K19003

    CPC分类号： H04L25/14

    摘要： According to some embodiments, provided are a first signal line, the first signal line coupled to a first repeater, the first repeater to convert a first signal from a received signal level to an output signal level, the first repeater to convert from a first signal level to a second signal level slower than from the second signal level to the first signal level, and a second signal line adjacent to the first signal line, the second signal line coupled to a second repeater adjacent to the first repeater, the second repeater to convert a second signal from a second received signal level to a second output signal level, the second repeater to convert from the first signal level to the second signal level slower than from the second signal level to the first signal level, wherein the received signal level is substantially equivalent to the second output signal level and wherein the second received signal level is substantially equivalent to the output signal level.