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1.发明授权Branch prediction technique using instruction for resetting result table pointer 有权分支预测技术，使用指令重置结果表指针公开(公告)号：US08078850B2
公开(公告)日：2011-12-13
申请号：US12108846
申请日：2008-04-24
CPC分类号： G06F9/3844 , G06F9/30145 , G06F9/322 , G06F9/3806
摘要： Methods, apparatus, and products for branch prediction in a computer processor are disclosed that include: recording for a sequence of occurrences of a branch, in an algorithm in which the branch occurs more than once, each result of the branch, including maintaining a pointer to a location of a most recently recorded result; resetting the pointer to a location of the first recorded result upon completion of the algorithm; and predicting subsequent results of the branch, in subsequent occurrences of the branch, in dependence upon the recorded results.
摘要翻译： 公开了一种用于在计算机处理器中进行分支预测的方法，装置和产品，包括：在分支出现多于一次的算法中记录分支出现次序，每个分支的结果包括保持指针 到最近记录的结果的位置; 完成算法后，将指针复位到第一记录结果的位置; 并根据记录的结果预测分支的随后的分支结果。
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公开(公告)号：US20090271597A1
公开(公告)日：2009-10-29
申请号：US12108846
申请日：2008-04-24
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/30145 , G06F9/322 , G06F9/3806
摘要： Methods, apparatus, and products for branch prediction in a computer processor are disclosed that include: recording for a sequence of occurrences of a branch, in an algorithm in which the branch occurs more than once, each result of the branch, including maintaining a pointer to a location of a most recently recorded result; resetting the pointer to a location of the first recorded result upon completion of the algorithm; and predicting subsequent results of the branch, in subsequent occurrences of the branch, in dependence upon the recorded results.
摘要翻译： 公开了一种用于在计算机处理器中进行分支预测的方法，装置和产品，包括：在分支出现多于一次的算法中记录分支出现次序，每个分支的结果包括保持指针 到最近记录的结果的位置; 完成算法后，将指针复位到第一记录结果的位置; 并根据记录的结果预测分支的随后的分支结果。
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3.发明授权Network on chip with low latency, high bandwidth application messaging interconnects that abstract hardware inter-thread data communications into an architected state of a processor 有权具有低延迟，高带宽应用程序消息互连的片上网络，将硬件线程间数据通信抽象为处理器的架构状态公开(公告)号：US07991978B2
公开(公告)日：2011-08-02
申请号：US12118272
申请日：2008-05-09
CPC分类号： G06F9/3889 , G06F9/30036 , G06F9/30043 , G06F9/38 , G06F9/3851 , G06F9/3879 , G06F9/3887 , G06F15/7825
摘要： Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, each of a plurality of the IP blocks including at least one computer processor, each such computer processor implementing a plurality of hardware threads of execution; low latency, high bandwidth application messaging interconnects; memory communications controllers; network interface controllers; and routers; each of the IP blocks adapted to a router through a separate one of the low latency, high bandwidth application messaging interconnects, a separate one of the memory communications controllers, and a separate one of the network interface controllers; each application messaging interconnect abstracting into an architected state of each processor, for manipulation by computer programs executing on the processor, hardware inter-thread communications among the hardware threads of execution; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers.
摘要翻译： 包括集成处理器（“IP”）块在片上网络（“NOC”）上的数据处理，多个IP块中的每一个包括至少一个计算机处理器，每个这样的计算机处理器实现多个执行的硬件线程 ; 低延迟，高带宽应用消息互连; 存储通信控制器; 网络接口控制器 和路由器; 每个IP块通过低延迟，高带宽应用消息互连中的单独一个，存储器通信控制器中的单独一个和网络接口控制器中的单独一个适配到路由器。 每个应用消息互连抽象成每个处理器的架构状态，用于由处理器上执行的计算机程序进行操纵，执行硬件线程之间的硬件跨线程通信; 每个存储器通信控制器控制IP块和存储器之间的通信; 每个网络接口控制器通过路由器控制IP间块通信。
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4.发明申请Network On Chip With Low Latency, High Bandwidth Application Messaging Interconnects That Abstract Hardware Inter-Thread Data Communications Into An Architected State of A Processor 有权具有低延迟，高带宽应用程序消息传递的片上网络将抽象硬件跨线数据通信转换为处理器的架构状态公开(公告)号：US20090282214A1
公开(公告)日：2009-11-12
申请号：US12118272
申请日：2008-05-09
CPC分类号： G06F9/3889 , G06F9/30036 , G06F9/30043 , G06F9/38 , G06F9/3851 , G06F9/3879 , G06F9/3887 , G06F15/7825
摘要： Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, each of a plurality of the IP blocks including at least one computer processor, each such computer processor implementing a plurality of hardware threads of execution; low latency, high bandwidth application messaging interconnects; memory communications controllers; network interface controllers; and routers; each of the IP blocks adapted to a router through a separate one of the low latency, high bandwidth application messaging interconnects, a separate one of the memory communications controllers, and a separate one of the network interface controllers; each application messaging interconnect abstracting into an architected state of each processor, for manipulation by computer programs executing on the processor, hardware inter-thread communications among the hardware threads of execution; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers.
摘要翻译： 包括集成处理器（“IP”）块在片上网络（“NOC”）上的数据处理，多个IP块中的每一个包括至少一个计算机处理器，每个这样的计算机处理器实现多个执行的硬件线程 ; 低延迟，高带宽应用消息互连; 存储通信控制器; 网络接口控制器 和路由器; 每个IP块通过低延迟，高带宽应用消息互连中的单独一个，存储器通信控制器中的单独一个和网络接口控制器中的单独一个适配于路由器。 每个应用消息互连抽象成每个处理器的架构状态，用于由处理器上执行的计算机程序进行操纵，执行硬件线程之间的硬件跨线程通信; 每个存储器通信控制器控制IP块和存储器之间的通信; 每个网络接口控制器通过路由器控制IP间块通信。
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公开(公告)号：US09176885B2
公开(公告)日：2015-11-03
申请号：US13355613
申请日：2012-01-23
CPC分类号： G06F12/0888 , G06F13/28
摘要： A circuit arrangement and method utilize cache injection logic to perform a cache inject and lock operation to inject a cache line in a cache memory and automatically lock the cache line in the cache memory in parallel with communication of the cache line to a main memory. The cache injection logic may additionally limit the maximum number of locked cache lines that may be stored in the cache memory, e.g., by aborting a cache inject and lock operation, injecting the cache line without locking, or unlocking and/or evicting another cache line in the cache memory.
摘要翻译： 电路装置和方法利用高速缓存注入逻辑来执行高速缓存注入和锁定操作，以将高速缓存行注入到高速缓冲存储器中，并且将高速缓存行与高速缓存行的通信并行地主动地锁定在高速缓存存储器中。 高速缓存注入逻辑可以另外限制可以存储在高速缓冲存储器中的锁定高速缓存行的最大数量，例如通过中止高速缓存注入和锁定操作，在不锁定的情况下注入高速缓存行，或者解锁和/或驱逐另一个高速缓存行 在缓存中。
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6.发明授权Providing performance tuned versions of compiled code to a CPU in a system of heterogeneous cores 有权将编译代码的性能调优版本提供给异构核心系统中的CPU公开(公告)号：US09195443B2
公开(公告)日：2015-11-24
申请号：US13352721
申请日：2012-01-18
CPC分类号： G06F8/443 , G06F8/47 , G06F8/54 , G06F9/44521 , G06F9/44542 , G06F9/5027
摘要： A compiler may optimize source code and any referenced libraries to execute on a plurality of different processor architecture implementations. For example, if a compute node has three different types of processors with three different architecture implementations, the compiler may compile the source code and generate three versions of object code where each version is optimized for one of the three different processor types. After compiling the source code, the resultant executable code may contain the necessary information for selecting between the three versions. For example, when a program loader assigns the executable code to the processor, the system determines the processor's type and ensures only the optimized version that corresponds to that type is executed. Thus, the operating system is free to assign the executable code to any of the different types of processors.
摘要翻译： 编译器可以优化源代码和任何引用的库以在多个不同的处理器架构实现上执行。 例如，如果计算节点具有三种不同类型的具有三种不同架构实现的处理器，则编译器可以编译源代码并生成三种版本的目标代码，其中每个版本针对三种不同处理器类型之一进行了优化。 在编译源代码之后，生成的可执行代码可能包含用于在三个版本之间进行选择的必要信息。 例如，当程序加载器将可执行代码分配给处理器时，系统确定处理器的类型并确保仅执行与该类型对应的优化版本。 因此，操作系统可以自由地将可执行代码分配给任何不同类型的处理器。
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公开(公告)号：US20130191600A1
公开(公告)日：2013-07-25
申请号：US13355613
申请日：2012-01-23
CPC分类号： G06F12/0888 , G06F13/28
摘要： A circuit arrangement and method utilize cache injection logic to perform a cache inject and lock operation to inject a cache line in a cache memory and automatically lock the cache line in the cache memory in parallel with communication of the cache line to a main memory. The cache injection logic may additionally limit the maximum number of locked cache lines that may be stored in the cache memory, e.g., by aborting a cache inject and lock operation, injecting the cache line without locking, or unlocking and/or evicting another cache line in the cache memory.
摘要翻译： 电路装置和方法利用高速缓存注入逻辑来执行高速缓存注入和锁定操作，以将高速缓存行注入到高速缓冲存储器中，并且将高速缓存行与高速缓存行的通信并行地主动地锁定在高速缓存存储器中。 高速缓存注入逻辑可以另外限制可以存储在高速缓冲存储器中的锁定高速缓存行的最大数量，例如通过中止高速缓存注入和锁定操作，在不锁定的情况下注入高速缓存行，或者解锁和/或驱逐另一个高速缓存行 在缓存中。
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公开(公告)号：US08990833B2
公开(公告)日：2015-03-24
申请号：US13330850
申请日：2011-12-20
CPC分类号： G06F9/546
摘要： A circuit arrangement, method, and program product for communicating data between hardware threads of a network on a chip processing unit utilizes shared inboxes to communicate data to pools of hardware threads. The associated hardware in the pools threads receive data packets from the shared inboxes in response to issuing work requests to an associated shared inbox. Data packets include a source identifier corresponding to a hardware thread from which the data packet was generated, and the shared inboxes may manage data packet distribution to associated hardware threads based on the source identifier of each data packet. A shared inbox may also manage workload distribution and uneven workload lengths by communicating data packets to hardware threads associated with the shared inbox in response to receiving work requests from associated hardware threads.
摘要翻译： 用于在芯片处理单元上的网络的硬件线程之间传送数据的电路装置，方法和程序产品利用共享的收件箱将数据传送到硬件线程池。 响应于向相关联的共享收件箱发出工作请求，池线程中的关联硬件从共享收件箱接收数据包。 数据分组包括对应于生成数据分组的硬件线程的源标识符，并且共享收件箱可以基于每个数据分组的源标识来管理相关联的硬件线程的数据分组分发。 通过将数据包传送到与共享收件箱相关联的硬件线程，响应于从相关联的硬件线程接收工作请求，共享收件箱还可以管理工作负载分布和不均衡的工作负载长度。
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9.发明申请PROVIDING PERFORMANCE TUNED VERSIONS OF COMPILED CODE TO A CPU IN A SYSTEM OF HETEROGENEOUS CORES 有权将编译代码的性能调整版本提供给异构系统中的CPU公开(公告)号：US20130185705A1
公开(公告)日：2013-07-18
申请号：US13352721
申请日：2012-01-18
CPC分类号： G06F8/443 , G06F8/47 , G06F8/54 , G06F9/44521 , G06F9/44542 , G06F9/5027
摘要： A compiler may optimize source code and any referenced libraries to execute on a plurality of different processor architecture implementations. For example, if a compute node has three different types of processors with three different architecture implementations, the compiler may compile the source code and generate three versions of object code where each version is optimized for one of the three different processor types. After compiling the source code, the resultant executable code may contain the necessary information for selecting between the three versions. For example, when a program loader assigns the executable code to the processor, the system determines the processor's type and ensures only the optimized version that corresponds to that type is executed. Thus, the operating system is free to assign the executable code to any of the different types of processors.
摘要翻译： 编译器可以优化源代码和任何引用的库以在多个不同的处理器架构实现上执行。 例如，如果计算节点具有三种不同类型的具有三种不同架构实现的处理器，则编译器可以编译源代码并生成三种版本的目标代码，其中每个版本针对三种不同处理器类型之一进行了优化。 在编译源代码之后，生成的可执行代码可能包含用于在三个版本之间进行选择的必要信息。 例如，当程序加载器将可执行代码分配给处理器时，系统确定处理器的类型并确保仅执行与该类型对应的优化版本。 因此，操作系统可以自由地将可执行代码分配给任何不同类型的处理器。
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10.发明授权Regular expression searches utilizing general purpose processors on a network interconnect 失效正则表达式在网络互连上搜索利用通用处理器公开(公告)号：US08719404B2
公开(公告)日：2014-05-06
申请号：US13036779
申请日：2011-02-28
IPC分类号： G06F15/177
CPC分类号： H04L67/28
摘要： A first hardware node in a network interconnect receives a data packet from a network. The first hardware node examines the data packet for a regular expression. In response to the first hardware node failing to identify the regular expression in the data packet, the data packet is forwarded to a second hardware node in the network interconnect for further examination of the data packet in order to search for the regular expression in the data packet.
摘要翻译： 网络互连中的第一个硬件节点从网络接收数据包。 第一个硬件节点检查正则表达式的数据包。 响应于第一硬件节点未能识别数据分组中的正则表达式，数据分组被转发到网络互连中的第二硬件节点，以进一步检查数据分组，以便搜索数据中的正则表达式 包。
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