公开(公告)号：US07933369B2

公开(公告)日：2011-04-26

申请号：US11635197

申请日：2006-12-07

申请人： Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

发明人： Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

IPC分类号： H04L27/08

CPC分类号： H04L27/0002 ,  H03G3/001 ,  H03G3/3068

摘要： Provided is an apparatus for automatic gain control (AGC) widely used in a receiver of a wireless communication system. The receiver of a wireless communication system includes: a step variable gain amplifier and an analog variable gain amplifier disposed in the path of a wireless signal and amplifying the wireless signal; an analog gain control unit for generating a gain control voltage for feedback-controlling an amplification value of the analog variable gain amplifier; a digital gain control unit for receiving the control voltage and generating a digital code determining an amplification value of the step variable gain amplifier. The apparatus for AGC constituted as described above can reduce power consumption and the number of devices by efficiently running an AGC loop in an analog domain, and can be embodied at low cost in a structure appropriately controlling the step gain amplifier and the analog gain amplifier.

摘要翻译： 提供了广泛用于无线通信系统的接收机中的自动增益控制（AGC）的装置。 无线通信系统的接收机包括：设置在无线信号的路径中的步进可变增益放大器和模拟可变增益放大器，并放大无线信号; 模拟增益控制单元，用于产生用于反馈控制模拟可变增益放大器的放大值的增益控制电压; 数字增益控制单元，用于接收控制电压并产生确定阶跃可变增益放大器的放大值的数字代码。 如上所述构成的AGC装置可以通过有效地运行模拟域中的AGC环路来降低功耗和装置数量，并且可以在适当地控制步进增益放大器和模拟增益放大器的结构中以低成本实现。

公开(公告)号：US08542773B2

公开(公告)日：2013-09-24

申请号：US12968731

申请日：2010-12-15

申请人： Hyun Kyu Yu ,  Jang Hong Choi ,  Hyun Ho Boo ,  Pil Jae Park ,  Mun Yang Park ,  Seong Do Kim ,  Sun Bo Shim ,  Song Cheol Hong

发明人： Hyun Kyu Yu ,  Jang Hong Choi ,  Hyun Ho Boo ,  Pil Jae Park ,  Mun Yang Park ,  Seong Do Kim ,  Sun Bo Shim ,  Song Cheol Hong

IPC分类号： H04L27/20 ,  H03C3/00 ,  H03M3/00 ,  H03M1/66

CPC分类号： H03M1/68 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747 ,  H03M3/50

摘要： A digital RF converter, a digital RF modulator, and a transmitter are provided. The digital RF converter includes a delta-sigma modulated bits (DSMB) sub-block that generates a current magnitude corresponding to least-significant n bits among input signals at a first sampling speed, a least-significant bit (LSB) sub-block that generates a current magnitude corresponding to intermediate k bits among the input signals at a second sampling speed lower than the first sampling speed, and a most-significant bit (MSB) sub block that generates a current magnitude corresponding to most-significant m bits among the inputs signals at the second sampling speed.

摘要翻译： 提供数字RF转换器，数字RF调制器和发射器。 该数字RF转换器包括一个Δ-Σ调制比特（DSMB）子块，其以第一采样速度在输入信号之间产生对应于最低有效n比特的当前幅度，最低有效位（LSB）子块， 以低于第一采样速度的第二采样速度产生对应于输入信号中的中间k位的电流幅度，以及最高有效位（MSB）子块，其产生对应于最高有效m位的当前幅度 以第二采样速度输入信号。

公开(公告)号：US08344772B2

公开(公告)日：2013-01-01

申请号：US12956498

申请日：2010-11-30

申请人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

IPC分类号： H03L7/06

CPC分类号： H03L7/095 ,  G04F10/005 ,  H03L7/085 ,  H03L7/103 ,  H03L2207/50

摘要： An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.

摘要翻译： 全数字锁相环（ADPLL）包括：相位计数器累积频率设定字值和数字控制振荡器（DCO）时钟的相位，并检测参考时钟和重新定时钟之间的精细相位差; 相位检测器，根据所述精细相位差检测补偿所述频率设定字值与所述DCO时钟之间的相位差的数字相位误差值，以检测数字相位误差值; 数字环路滤波器滤除数字相位误差值并控制PLL的操作特性; 锁定检测器，根据数字环路滤波器的输出产生锁定指示信号; 数字控制振荡器根据数字环路滤波器的输出改变DCO时钟的频率; 以及重新计时的时钟发生器，通过以低频再定时DCO时钟产生重定时钟。

公开(公告)号：US20110150125A1

公开(公告)日：2011-06-23

申请号：US12968731

申请日：2010-12-15

申请人： Hyun Kyu YU ,  Jang Hong Choi ,  Hyun Ho Boo ,  Pil Jae Park ,  Mun Yang Park ,  Seong Do Kim ,  Sun Bo Shim ,  Song Cheol Hong

发明人： Hyun Kyu YU ,  Jang Hong Choi ,  Hyun Ho Boo ,  Pil Jae Park ,  Mun Yang Park ,  Seong Do Kim ,  Sun Bo Shim ,  Song Cheol Hong

IPC分类号： H04L27/00 ,  H03M3/02 ,  H03M1/66

CPC分类号： H03M1/68 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747 ,  H03M3/50

摘要： There are provided a digital RF converter capable of improving a dynamic range and a signal to noise ratio of a transmitter and a digital RF modulator and a transmitter including the same. The digital RF converter may include: a delta-sigma modulated bits (DSMB) sub-block that generates a current magnitude corresponding to least-significant n bits among input signals at a first sampling speed; a least-significant bit (LSB) sub-block that generates a current magnitude corresponding to intermediate k bits among the input signals at a second sampling speed lower than the first sampling speed; and a most-significant bit (MSB) sub block that generates a current magnitude corresponding to most-significant m bits among the inputs signals at the second sampling speed.

摘要翻译： 提供了能够改善发射机和数字RF调制器的动态范围和信噪比的数字RF转换器，以及包括该数字RF转换器的发射机。 数字RF转换器可以包括：Δ-Σ调制比特（DSMB）子块，其以第一采样速度在输入信号中产生对应于最低有效n比特的电流幅度; 最低有效位（LSB）子块，其以比第一采样速度低的第二采样速度在输入信号中产生对应于中间k位的电流幅度; 和最高有效位（MSB）子块，其以第二采样速度在输入信号中产生对应于最高有效m位的电流幅度。

公开(公告)号：US20110148490A1

公开(公告)日：2011-06-23

申请号：US12956498

申请日：2010-11-30

申请人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

IPC分类号： H03L7/08 ,  H03M1/50

CPC分类号： H03L7/095 ,  G04F10/005 ,  H03L7/085 ,  H03L7/103 ,  H03L2207/50

摘要： An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.

摘要翻译： 全数字锁相环（ADPLL）包括：相位计数器累积频率设定字值和数字控制振荡器（DCO）时钟的相位，并检测参考时钟和重新定时钟之间的精细相位差; 相位检测器，根据所述精细相位差检测补偿所述频率设定字值与所述DCO时钟之间的相位差的数字相位误差值，以检测数字相位误差值; 数字环路滤波器滤除数字相位误差值并控制PLL的操作特性; 锁定检测器，根据数字环路滤波器的输出产生锁定指示信号; 数字控制振荡器根据数字环路滤波器的输出来改变DCO时钟的频率; 以及重新计时的时钟发生器，通过以低频再定时DCO时钟产生重定时钟。

公开(公告)号：US20120146852A1

公开(公告)日：2012-06-14

申请号：US13316381

申请日：2011-12-09

申请人： Pil Jae Park ,  Seong Do Kim ,  Sung Chul Woo ,  Hyun Kyu Yu

发明人： Pil Jae Park ,  Seong Do Kim ,  Sung Chul Woo ,  Hyun Kyu Yu

IPC分类号： G01S7/285

CPC分类号： G01S7/292

摘要： A pulse radar receiver includes a power splitter configured to split a transmit (TX) trigger signal for generating a TX pulse, a phase-locked loop (PLL) configured to receive a division ratio and the TX trigger signal split by the power splitter, and generate a sampling frequency, and a sampler configured to sample a reflected wave received through an RX antenna, according to the sampling frequency generated by the PLL. Accordingly, it is possible to provide a high distance resolution by generating a sampling frequency with a difference from a TX pulse to sample a reflected wave received through an RX antenna. Thus, it is possible to overcome a limitation in the distance resolution due to the pulse width and to measure a minute movement at a short distance. Therefore, the pulse radar receiver is applicable to high range resolution radar applications such as a living body measuring radar.

摘要翻译： 脉冲雷达接收机包括：功率分配器，被配置为分离用于产生TX脉冲的发射（TX）触发信号;配置为接收分频比的锁相环（PLL）和由功率分配器分离的TX触发信号;以及 产生采样频率，并且采样器被配置为根据由PLL产生的采样频率对通过RX天线接收的反射波进行采样。 因此，通过产生与TX脉冲不同的采样频率来采样通过RX天线接收的反射波，可以提供高距离分辨率。 因此，可以克服由于脉冲宽度导致的距离分辨率的限制并且能够在短距离处测量微小的移动。 因此，脉冲雷达接收机适用于诸如生物体测量雷达的高范围分辨率雷达应用。

公开(公告)号：US08060020B2

公开(公告)日：2011-11-15

申请号：US12628684

申请日：2009-12-01

申请人： Seong Do Kim ,  Ja Yol Lee ,  Jae Hoon Shim ,  Hyun Kyu Yu

发明人： Seong Do Kim ,  Ja Yol Lee ,  Jae Hoon Shim ,  Hyun Kyu Yu

IPC分类号： H04B1/00

CPC分类号： H04B1/123

摘要： An apparatus and method for removing an interference signal using a selective frequency phase converter are disclosed. The apparatus for removing an interference signal using a selective frequency phase converter includes: a first phase converter configured to convert a phase of a received RF signal to differentially output first and second signals having a phase difference of 180° from each other; a second phase converter configured to receive the first signal and selectively convert the phase of a particular frequency band; a third phase converter configured to receive the second signal and selectively convert the phase of a particular frequency band; a timing controller configured to correct a signal delay time between the output from the second phase converter and that of the third phase converter; and an adder configured to add an output from the second phase converter and an output from the third phase converter, wherein the second and third phase converters phase-convert the first and second signals such that the phases of the signals of the particular frequency bands do not have a phase difference of 180° from each other.

摘要翻译： 公开了一种使用选择性频率相位变换器去除干扰信号的装置和方法。 使用选择性频率相位变换器去除干扰信号的装置包括：第一相位转换器，被配置为将接收的RF信号的相位转换为差分地输出具有彼此相差180°的第一和第二信号; 第二相转换器，被配置为接收第一信号并选择性地转换特定频带的相位; 配置为接收所述第二信号并选择性地转换特定频带的相位的第三相位转换器; 定时控制器，被配置为校正来自第二相位转换器的输出和第三相位转换器的输出之间的信号延迟时间; 以及加法器，被配置为将来自第二相位转换器的输出和来自第三相位转换器的输出相加，其中第二和第三相位转换器对第一和第二信号进行相位转换，使得特定频带的信号的相位做 彼此之间没有180°的相位差。

公开(公告)号：US07626476B2

公开(公告)日：2009-12-01

申请号：US11690219

申请日：2007-03-23

申请人： Cheon Soo Kim ,  Myung Shin Kwak ,  Seong Do Kim ,  Mun Yang Park ,  Hyun Kyu Yu ,  Hee Bum Jung

发明人： Cheon Soo Kim ,  Myung Shin Kwak ,  Seong Do Kim ,  Mun Yang Park ,  Hyun Kyu Yu ,  Hee Bum Jung

IPC分类号： H01P3/08

CPC分类号： H01P3/003

摘要： A coplanar waveguide CPW using multi-layer interconnection CMOS technology is provided. In the CPW including an interlayer insulator disposed on a substrate, metal multilayers disposed on the interlayer insulator, and a ground line-a signal line-a ground line formed of an uppermost metal layer, when a ground line of a lowermost layer is connected to the ground line of the uppermost layer, intermediate metal layers are designed to gradually increase or decrease in width, or to be uneven so as to maximize an area where an ultra-high frequency spreads, thereby minimizing CPW loss and maximizing a slow wave effect. As a result, it is possible to improve performance of an ultra-high frequency circuit and miniaturize the circuit.

摘要翻译： 提供了一种使用多层互连CMOS技术的共面波导CPW。 在包括设置在基板上的层间绝缘体的CPW中，设置在层间绝缘体上的金属多层和最下层的接地线的接地线 - 信号线 - 由最上层金属层形成的接地线连接到 最上层的地线，中间金属层被设计成逐渐增加或减小宽度或不均匀，以便使超高频率扩展的面积最大化，由此最小化CPW损耗并最大化慢波效应。 结果，可以提高超高频电路的性能并使电路小型化。

公开(公告)号：US08754806B2

公开(公告)日：2014-06-17

申请号：US13316381

申请日：2011-12-09

申请人： Pil Jae Park ,  Seong Do Kim ,  Sung Chul Woo ,  Hyun Kyu Yu

发明人： Pil Jae Park ,  Seong Do Kim ,  Sung Chul Woo ,  Hyun Kyu Yu

IPC分类号： G01S7/285 ,  G01S7/00 ,  G01S13/10

CPC分类号： G01S7/292

摘要： A pulse radar receiver includes a power splitter configured to split a transmit (TX) trigger signal for generating a TX pulse, a phase-locked loop (PLL) configured to receive a division ratio and the TX trigger signal split by the power splitter, and generate a sampling frequency, and a sampler configured to sample a reflected wave received through an RX antenna, according to the sampling frequency generated by the PLL. Accordingly, it is possible to provide a high distance resolution by generating a sampling frequency with a difference from a TX pulse to sample a reflected wave received through an RX antenna. Thus, it is possible to overcome a limitation in the distance resolution due to the pulse width and to measure a minute movement at a short distance. Therefore, the pulse radar receiver is applicable to high range resolution radar applications such as a living body measuring radar.

摘要翻译： 脉冲雷达接收机包括：功率分配器，被配置为分离用于产生TX脉冲的发射（TX）触发信号;配置为接收分频比的锁相环（PLL）和由功率分配器分离的TX触发信号;以及 产生采样频率，并且采样器被配置为根据由PLL产生的采样频率对通过RX天线接收的反射波进行采样。 因此，通过产生与TX脉冲不同的采样频率来采样通过RX天线接收的反射波，可以提供高距离分辨率。 因此，可以克服由于脉冲宽度导致的距离分辨率的限制并且能够在短距离处测量微小的移动。 因此，脉冲雷达接收机适用于诸如生物体测量雷达的高范围分辨率雷达应用。

公开(公告)号：US08013641B1

公开(公告)日：2011-09-06

申请号：US13098332

申请日：2011-04-29

申请人： Ja Yol Lee ,  Seong Do Kim ,  Mun Yang Park ,  Cheon Soo Kim ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Seong Do Kim ,  Mun Yang Park ,  Cheon Soo Kim ,  Hyun Kyu Yu

IPC分类号： H03B21/00

CPC分类号： H03L7/16 ,  H03L7/095 ,  H03L7/099 ,  H03L7/103 ,  H03L2207/50

摘要： There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.

摘要翻译： 提供了数字锁定检测器和使用该锁定检测器的频率合成器。 数字锁定检测器包括：接收多个控制位的比较器单元，并产生一个位信号以注意多个控制位的锁定状态; 延迟单元块，其基于所述位信号生成多个延迟信号，并通过组合所述位信号和所述多个延迟信号来输出时钟信号; 以及检测单元，其检测所述时钟信号的移位时间，并根据所述检测结果生成锁定指示信号。