公开(公告)号：US09728549B2

公开(公告)日：2017-08-08

申请号：US14974567

申请日：2015-12-18

Applicant: Jang-Gn Yun ,  Sunghoi Hur ,  Jaesun Yun ,  Joon-Sung Lim

Inventor： Jang-Gn Yun ,  Sunghoi Hur ,  Jaesun Yun ,  Joon-Sung Lim

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

CPC classification number: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

Abstract: A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

公开(公告)号：US10043816B2

公开(公告)日：2018-08-07

申请号：US14474867

申请日：2014-09-02

Applicant: Kim Taekyung ,  Kwang Soo Seol ,  Seong Soon Cho ,  Sunghoi Hur ,  Jintae Kang

Inventor： Kim Taekyung ,  Kwang Soo Seol ,  Seong Soon Cho ,  Sunghoi Hur ,  Jintae Kang

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/4763 ,  H01L27/1157 ,  H01L29/423 ,  H01L27/11519 ,  H01L27/11582 ,  H01L29/792

Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.

公开(公告)号：US20140061757A1

公开(公告)日：2014-03-06

申请号：US13971279

申请日：2013-08-20

Applicant: SUNGGIL KIM ,  Sunghoi Hur ,  Jung-Hwan Kim ,  HongSuk Kim ,  Guk-Hyon Yon ,  JaeHo Choi

Inventor： SUNGGIL KIM ,  Sunghoi Hur ,  Jung-Hwan Kim ,  HongSuk Kim ,  Guk-Hyon Yon ,  JaeHo Choi

IPC: H01L29/788 ,  H01L29/66

CPC classification number: H01L29/788 ,  H01L21/764 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11582 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

Abstract: A semiconductor device includes a semiconductor substrate having a plurality of active regions defined by a trench. A gate electrode crosses the plurality of active regions. A plurality of charge storing cells is disposed between the gate electrode and each of the plurality of active regions. A porous insulating layer is disposed between the gate electrode and the plurality of charge storing cells. The porous insulating layer includes a portion extended over the trench. An air gap is disposed between the extended portion of the porous insulating layer and a bottom surface of the trench.

Abstract translation: 半导体器件包括具有由沟槽限定的多个有源区的半导体衬底。 栅电极与多个有源区交叉。 多个电荷存储单元设置在栅电极和多个有源区域中的每一个之间。 多孔绝缘层设置在栅电极和多个电荷存储单元之间。 多孔绝缘层包括在沟槽上延伸的部分。 空隙设置在多孔绝缘层的延伸部分和沟槽的底表面之间。

公开(公告)号：US20130248983A1

公开(公告)日：2013-09-26

申请号：US13898032

申请日：2013-05-20

Applicant: Younggoan Jang ,  Sunghoi Hur ,  Jinho Kim ,  Sunil Shim ,  Su-Youn Yi ,  HuiChang Moon

Inventor： Younggoan Jang ,  Sunghoi Hur ,  Jinho Kim ,  Sunil Shim ,  Su-Youn Yi ,  HuiChang Moon

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device includes word lines and gate interlayer insulation layers that are alternatively stacked on a semiconductor substrate while extending in a horizontal direction, a vertical channel layer that faces the word lines and extends upwardly from the semiconductor substrate, and a channel pad that extends from the vertical channel layer and is disposed on an uppermost gate interlayer insulation layer of the gate interlayer insulation layers.

Abstract translation: 一种三维半导体存储器件包括字形线和栅极层间绝缘层，其交替地层叠在半导体衬底上，同时在水平方向上延伸，垂直沟道层面向字线并从半导体衬底向上延伸，并且沟道 衬垫，其从垂直沟道层延伸并且设置在栅极层间绝缘层的最上层的栅极层间绝缘层上。

公开(公告)号：US20130171806A1

公开(公告)日：2013-07-04

申请号：US13779334

申请日：2013-02-27

Applicant: Sunil Shim ,  Sunghoi Hur ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho

Inventor： Sunil Shim ,  Sunghoi Hur ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho

IPC: H01L21/02

CPC classification number: H01L21/02365 ,  H01L21/02697 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

Abstract: Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level.

Abstract translation: 提供一种三维半导体存储器件。 三维半导体存储器件包括具有包括一对子单元区域的单元阵列区域和插入该一对子单元区域之间的带状区域的基板。 多个子栅极依次层叠在每个子单元区域中的衬底上，并且互连电连接到延伸到捆扎区域中的堆叠子栅极的延伸部分。 每个互连电连接到分别设置在一对子单元区域中并且位于同一电平的子栅极的延伸部分。

公开(公告)号：US08445954B2

公开(公告)日：2013-05-21

申请号：US12592404

申请日：2009-11-24

Applicant: Younggoan Jang ,  Sunghoi Hur ,  Jinho Kim ,  Sunil Shim ,  Su-Youn Yi ,  HuiChang Moon

Inventor： Younggoan Jang ,  Sunghoi Hur ,  Jinho Kim ,  Sunil Shim ,  Su-Youn Yi ,  HuiChang Moon

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device includes word lines and gate interlayer insulation layers that are alternatively stacked on a semiconductor substrate while extending in a horizontal direction, a vertical channel layer that faces the word lines and extends upwardly from the semiconductor substrate, and a channel pad that extends from the vertical channel layer and is disposed on an uppermost gate interlayer insulation layer of the gate interlayer insulation layers.

公开(公告)号：US08406062B2

公开(公告)日：2013-03-26

申请号：US12917072

申请日：2010-11-01

Applicant: Kwnag Soo Seol ,  Jungdal Choi ,  Sunghoi Hur

Inventor： Kwnag Soo Seol ,  Jungdal Choi ,  Sunghoi Hur

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/0483 ,  G11C16/12 ,  G11C16/30

Abstract: A memory system, including a nonvolatile memory device, a charge recycler configured to discharge charges from the nonvolatile memory device and recycle the discharged charges, and a controller configured to control the nonvolatile memory device and the charge recycler, wherein the controller controls the charge recycler to recycle the discharged charges, wherein during the recycling the charge recycler charges the charges discharged from the nonvolatile memory device.

Abstract translation: 一种存储器系统，包括非易失性存储器件，电荷回收器，被配置为从非易失性存储器件放电电荷并再循环放电的电荷;以及控制器，被配置为控制非易失性存储器件和电荷回收器，其中控制器控制电荷回收器 以再循环排出的电荷，其中在再循环期间，电荷回收器对从非易失性存储器件排出的电荷进行充电。

公开(公告)号：US08278170B2

公开(公告)日：2012-10-02

申请号：US13165576

申请日：2011-06-21

Applicant: Changhyun Lee ,  Sunil Shim ,  Jaehoon Jang ,  Sunghoi Hur ,  Hansoo Kim ,  Kihyun Kim

Inventor： Changhyun Lee ,  Sunil Shim ,  Jaehoon Jang ,  Sunghoi Hur ,  Hansoo Kim ,  Kihyun Kim

IPC: H01L21/336

CPC classification number: G11C16/28 ,  G11C16/14 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/7889 ,  H01L29/7926

Abstract: Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.

Abstract translation: 形成根据本发明的实施例的非易失性存储器件的方法包括形成非易失性存储器单元的高度集成的垂直堆叠的技术。 这些垂直堆叠的存储器单元可以利用虚拟存储器单元来补偿当相对大量的存储单元垂直地堆叠在半导体衬底上时使用电连接的多个垂直子串的过程伪像，否则会产生相对较差的功能性存储单元串 系列。

公开(公告)号：US20110169068A1

公开(公告)日：2011-07-14

申请号：US12986553

申请日：2011-01-07

Applicant: JAEDUK LEE ,  Albert Fayrushin ,  ByungKyu Cho ,  Jungdal Choi ,  Sunghoi Hur ,  Kwang Soo Seol ,  Dohyun Lee

Inventor： JAEDUK LEE ,  Albert Fayrushin ,  ByungKyu Cho ,  Jungdal Choi ,  Sunghoi Hur ,  Kwang Soo Seol ,  Dohyun Lee

IPC: H01L29/788

CPC classification number: H01L29/42336 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42352 ,  H01L29/7881 ,  H01L29/792

Abstract: Provided are nonvolatile memory devices and a method of forming the same. A tunnel insulating pattern is provided on a substrate, and a floating gate is provided on the tunnel insulating pattern. A floating gate cap having a charge trap site is provided on the floating gate, and a gate dielectric pattern is provided on the floating gate cap. A control gate is provided on the gate dielectric pattern.

Abstract translation: 提供了非易失性存储器件及其形成方法。 隧道绝缘图案设置在基板上，并且浮动栅极设置在隧道绝缘图案上。 在浮置栅极上设置具有电荷陷阱位置的浮动栅极盖，并且在浮动栅极盖上设置栅极电介质图案。 控制栅极设置在栅极电介质图案上。

公开(公告)号：US09012977B2

公开(公告)日：2015-04-21

申请号：US14154834

申请日：2014-01-14

Applicant: Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Su-Youn Yi ,  Jaehoon Jang ,  Sunghoi Hur

Inventor： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Su-Youn Yi ,  Jaehoon Jang ,  Sunghoi Hur

IPC: H01L29/792 ,  H01L29/66 ,  H01L27/02 ,  H01L27/115

CPC classification number: H01L27/0207 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

Abstract: Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.

Abstract translation: 提供了一种半导体存储器件。 在半导体存储器件中，下部选择栅极控制限定在半导体衬底上的第一沟道区和限定在设置在半导体衬底上的有源图案的下部的第二沟道区。 第一沟道区的第一阈值电压不同于第二沟道区的第二阈值电压。