公开(公告)号：US12100709B2

公开(公告)日：2024-09-24

申请号：US18480552

申请日：2023-10-04

Applicant: Japan Display Inc.

Inventor： Isao Suzumura ,  Kazufumi Watabe ,  Yoshinori Ishii ,  Hidekazu Miyake ,  Yohei Yamaguchi

IPC: H01L27/12 ,  G02F1/133 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/24 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H10K59/121

CPC classification number: H01L27/1225 ,  G02F1/13306 ,  G02F1/136209 ,  G02F1/1368 ,  H01L27/1251 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/78633 ,  H01L29/78675 ,  H01L29/7869 ,  G02F1/13685 ,  G02F2202/10 ,  G02F2202/104 ,  H10K59/1213

Abstract: The object of the present invention is to make it possible to form an LTPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor 109. An oxide film 110 as an insulating material is formed on the oxide semiconductor 109. A gate electrode 111 is formed on the oxide film 110. A first electrode 115 is connected to a drain of the first TFT via a first through hole formed in the oxide film 110. A second electrode 116 is connected to a source of the first TFT via a second through hole formed in the oxide film 110.

公开(公告)号：US11056514B2

公开(公告)日：2021-07-06

申请号：US15659796

申请日：2017-07-26

Applicant: Japan Display Inc.

Inventor： Yoshinori Ishii ,  Kazufumi Watabe ,  Hidekazu Miyake

IPC: H01L27/12 ,  G02F1/13 ,  G02F1/1333 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/32 ,  H01L51/52 ,  H01L51/56 ,  G02F1/1343

Abstract: Separation of wirings formed on an organic passivation film is prevented in an organic EL display device or a liquid crystal display device. The organic EL display device includes a TFT formed on a substrate and an organic passivation film formed to cover the TFT. An intermediate film containing SiO or SiN is formed to cover the organic passivation film. An insulation film formed with an organic material is formed on the intermediate film. A reflective electrode is formed on the intermediate film. The reflective electrode is connected to the TFT via a through-hole formed in the organic passivation film and a through-hole formed in the intermediate film.

公开(公告)号：US10403652B2

公开(公告)日：2019-09-03

申请号：US15661086

申请日：2017-07-27

Applicant: Japan Display Inc.

Inventor： Yoshinori Ishii ,  Kazufumi Watabe ,  Hidekazu Miyake

IPC: H01L27/12 ,  H01L33/00 ,  H01L29/786 ,  G02F1/13 ,  G02F1/1333 ,  G02F1/1368 ,  H01L27/32 ,  H01L51/52 ,  G02F1/1362

Abstract: An organic EL display device has a semiconductor circuit substrate comprising a TFT and an organic passivation layer thereon. An AlO layer is formed over the organic passivation layer, and an electrode layer is formed on the AlO layer. The electrode layer connects with TFT via a through hole formed in the AlO layer and in the organic passivation layer.

公开(公告)号：US09709853B2

公开(公告)日：2017-07-18

申请号：US14480804

申请日：2014-09-09

Applicant: Japan Display Inc.

Inventor： Norihiro Uemura ,  Hidekazu Miyake ,  Isao Suzumura ,  Yohei Yamaguchi ,  Toshiki Kaneko

IPC: G02F1/1345 ,  G02F1/1337 ,  G02F1/1362 ,  G02F1/1333

CPC classification number: G02F1/133788 ,  G02F1/136209 ,  G02F2001/133388

Abstract: To maintain good operation of a peripheral circuit using an oxide thin film transistor in a liquid crystal display panel to which photo alignment is applied, the liquid crystal display panel includes: a transparent substrate provided with an oxide thin film transistor in the periphery of a pixel portion in which pixel electrodes are arranged, to control the pixel electrodes; and an alignment film to align liquid crystal provided in the pixel portion. The alignment film is subjected to photo alignment treatment by ultraviolet irradiation. Further, an ultraviolet absorbing layer is provided so as to cover the oxide thin film transistor. For example, an alignment film is used for the ultraviolet absorbing layer to absorb the ultraviolet light for the photo aliment treatment of the alignment film, in the peripheral circuit portion for controlling the pixel electrodes, thereby preventing the threshold voltage of the oxide thin film transistor from shifting.

公开(公告)号：US09660039B2

公开(公告)日：2017-05-23

申请号：US15062887

申请日：2016-03-07

Applicant: Japan Display Inc.

Inventor： Hidekazu Miyake ,  Arichika Ishida ,  Hiroto Miyake ,  Isao Suzumura ,  Yohei Yamaguchi

IPC: H01L29/49 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/78696

Abstract: According to one embodiment, a thin-film transistor includes a semiconductor layer SC including a channel region, and a source region and a drain region on both sides of the channel region, a gate electrode GE, a first electrode SE connected to the source region via a first contact hole CH1, a second electrode DE connected to the drain region via a second contact hole CH2, a source line connected to the first electrode, and a drain line connected to the second electrode. A distance from the first and second contact holes to an end of the respective regions in a direction of a channel width is greater than or equal to 5 μm and less than or equal to 30 μm. The source line and the drain line extend in directions different from each other.

公开(公告)号：US09620526B2

公开(公告)日：2017-04-11

申请号：US15015445

申请日：2016-02-04

Applicant: Japan Display Inc.

Inventor： Isao Suzumura ,  Norihiro Uemura ,  Hidekazu Miyake ,  Yohei Yamaguchi

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L21/473 ,  H01L21/02 ,  H01L21/3213

CPC classification number: H01L27/1225 ,  H01L21/02071 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/32138 ,  H01L21/32139 ,  H01L21/473 ,  H01L27/1248 ,  H01L27/127 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

Abstract: There is provided a bottom gate channel etched thin film transistor that can suppress initial Vth depletion and a Vth shift. A thin film transistor is formed, including a gate electrode interconnection disposed on a substrate, a gate insulating film, an oxide semiconductor layer to be a channel layer, a stacked film of a source electrode interconnection and a first hard mask layer, a stacked film of a drain electrode interconnection and a second hard mask layer, and a protective insulating film.

公开(公告)号：US09613860B2

公开(公告)日：2017-04-04

申请号：US14996323

申请日：2016-01-15

Applicant: Japan Display Inc.

Inventor： Isao Suzumura ,  Arichika Ishida ,  Hidekazu Miyake ,  Hiroto Miyake ,  Yohei Yamaguchi

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/02 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786 ,  H01L29/49 ,  H01L21/78

CPC classification number: H01L21/76895 ,  H01L21/022 ,  H01L21/32136 ,  H01L21/465 ,  H01L21/78 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869

Abstract: According to one embodiment, a method of manufacturing a thin-film transistor includes forming a semiconductor layer on a gate electrode with an insulating layer 12 being interposed, forming interconnect formation layers on the semiconductor layer, forming a plurality of interconnects and electrodes by patterning the interconnect formation layers through etching, patterning the semiconductor layer in an island shape through etching after forming the electrodes, exposing a channel region of the semiconductor layer by etching a part of the electrodes on the semiconductor layer, and forming a protective layer so as to overlap the interconnects, the electrodes and the semiconductor layer having the island shape.

公开(公告)号：US11521990B2

公开(公告)日：2022-12-06

申请号：US17336620

申请日：2021-06-02

Applicant: Japan Display Inc.

Inventor： Isao Suzumura ,  Kazufumi Watabe ,  Yoshinori Ishii ,  Hidekazu Miyake ,  Yohei Yamaguchi

IPC: H01L27/12 ,  H01L27/32 ,  H01L29/786 ,  H01L29/51 ,  H01L29/24 ,  G02F1/1368 ,  G02F1/133 ,  G02F1/1362 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49

Abstract: The object of the present invention is to make it possible to form an LTPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor 109. An oxide film 110 as an insulating material is formed on the oxide semiconductor 109. A gate electrode 111 is formed on the oxide film 110. A first electrode 115 is connected to a drain of the first. TFT via a first through hole formed in the oxide film 110. A second electrode 116 is connected to a source of the first TFT via a second through hole formed in the oxide film 110.

公开(公告)号：US20210141256A1

公开(公告)日：2021-05-13

申请号：US17126112

申请日：2020-12-18

Applicant: Japan Display Inc.

Inventor： Yohei YAMAGUCHI ,  Arichika Ishida ,  Hidekazu Miyake ,  Hiroto Miyake ,  Isao Suzumura

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L27/12 ,  H01L29/786 ,  G02F1/1343

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first metal layer on the insulating substrate, a first insulating layer on the insulating substrate and the first metal layer, a semiconductor layer on the first insulating layer, a second insulating layer on the semiconductor layer and the first insulating layer, a second metal layer on the second insulating layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer. The first metal layer overlaps the second metal layer. A third metal layer contacts a top surface of the second metal layer and a top surface of the first metal layer.

公开(公告)号：US10833134B2

公开(公告)日：2020-11-10

申请号：US16715008

申请日：2019-12-16

Applicant: Japan Display Inc.

Inventor： Hidekazu Miyake ,  Kazufumi Watabe ,  Yoshinori Ishii

IPC: H01L27/32 ,  G06F3/041 ,  G06F3/044

Abstract: An EL display device includes a TFT substrate on which a scanning line extends in a first direction, a video signal line extends in a second direction, and an EL element having an anode, a luminous layer and a cathode. A protective film covers the scanning line, the video signal line and the EL element. A touch panel detection electrode is disposed above the protective film, and connected to a wiring which is disposed under the protective film via a through hole of the protective film. The touch panel detection electrode has an angle to intersect with the video signal line.