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1.发明授权Scalable on-chip bus performance monitoring synchronization mechanism and method of use 有权可扩展的片上总线性能监控同步机制和使用方法公开(公告)号：US06857029B2
公开(公告)日：2005-02-15
申请号：US10137084
申请日：2002-04-30
申请人： Jaya Prakash Subramaniam Ganasan , Adger Erik Harvin, III , Richard Gerard Hofmann , Perry Willmann Remaklus, Jr.
发明人： Jaya Prakash Subramaniam Ganasan , Adger Erik Harvin, III , Richard Gerard Hofmann , Perry Willmann Remaklus, Jr.
CPC分类号： G06F1/12
摘要： A bus performance monitoring mechanism for systems on a chip (SOC) is disclosed. The system comprises a muxing logic adapted to be coupled to a plurality of master devices, a plurality of slave devices, a plurality of generic signals and a plurality of control signals. The monitoring mechanism includes a plurality of control registers coupled to the muxing logic to allow for the selection of master, slave, generic and pipeline stage events to be counted. Finally, the monitoring mechanism includes synchronizing logic coupled to the plurality of registers for providing and receiving synchronizing signals to and from the monitors coupled thereto to allow for scalability. The scalable on-chip bus performance monitoring system in accordance with the present invention performs on-chip bus monitoring within a SOC implementation, while eliminating the pitfalls as described above. Through a minimalistic design approach, scalability is easily accomplished through the concept of using multiple monitor instances of these monitoring mechanisms within an SOC design while maintaining synchronization among them. Should an SOC design increase in size, scalability is achieved by simply adding additional monitor instance(s). The multiple monitor instances could then be connected in a “lego-like” fashion, allowing each to operate independently, or concurrently with one another via a scalable synchronization technique. For these designs where multiple monitor instances may be required, this enhances wireability by allowing the SOC designer to scatter the monitor instance locations virtually anywhere within the smaller areas of unused chip space, and simply wire the synchronization signals among the monitor instances to allow for synchronous operation.
摘要翻译： 公开了一种用于芯片系统（SOC）的总线性能监视机制。 该系统包括适于耦合到多个主设备，多个从设备，多个通用信号和多个控制信号的多路复用逻辑。 监视机制包括耦合到多路复用逻辑的多个控制寄存器，以允许对主，从，通用和流水线级事件的选择进行计数。 最后，监视机制包括与多个寄存器耦合的同步逻辑，用于提供和接收与耦合到其的监视器同步信号以允许可扩展性。 根据本发明的可扩展的片上总线性能监视系统在SOC实现中执行片上总线监视，同时消除如上所述的陷阱。 通过简约的设计方法，可以通过在SOC设计中使用这些监视机制的多个监视器实例，同时保持它们之间的同步来实现可扩展性。 如果SOC设计的大小增加，则通过简单地添加附加的监视器实例来实现可扩展性。 然后，多个监视器实例可以以“lego-like”的方式连接，允许每个监视器实例通过可伸缩的同步技术独立地或彼此并行操作。 对于可能需要多个监视器实例的这些设计，通过允许SOC设计人员将监视器实例位置实际上分散在未使用的芯片空间的较小区域内的任何位置，从而提高了可线性，并且简单地将监视器实例之间的同步信号连接起来以允许同步 操作。
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公开(公告)号：US07921249B2
公开(公告)日：2011-04-05
申请号：US12561381
申请日：2009-09-17
IPC分类号： G06F13/00
CPC分类号： G06F13/1621 , G06F9/52 , G06F9/522
摘要： The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being produced before the execution of all memory access requests issued by the master device to the memory before the memory barrier.
摘要翻译： 本公开涉及一种弱有序处理系统和在弱有序处理系统中执行存储障碍的方法。 处理系统包括存储器和被配置为向存储器发出存储器访问请求（包括存储器障碍）的主设备。 处理系统还包括被配置为提供主设备对存储器的访问的从设备，从设备还被配置为产生指示由主设备发布的存储器障碍施加的排序约束将被强制的信号，信号 在执行由主设备发出的所有存储器访问请求之前在存储器屏障之前被产生到存储器。
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3.发明授权Efficient execution of memory barrier bus commands with order constrained memory accesses 有权具有订单约束的存储器访问的存储器障碍总线命令的高效执行公开(公告)号：US07917676B2
公开(公告)日：2011-03-29
申请号：US11397287
申请日：2006-04-04
IPC分类号： G06F13/00
CPC分类号： G06F13/1621 , G06F9/52 , G06F9/522
摘要： The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being produced before the execution of all memory access requests issued by the master device to the memory before the memory barrier.
摘要翻译： 本公开涉及一种弱有序处理系统和在弱有序处理系统中执行存储障碍的方法。 处理系统包括存储器和被配置为向存储器发出存储器访问请求（包括存储器障碍）的主设备。 处理系统还包括被配置为提供主设备对存储器的访问的从设备，从设备还被配置为产生指示由主设备发布的存储器障碍施加的排序约束将被强制的信号，信号 在执行由主设备发出的所有存储器访问请求之前在存储器屏障之前被产生到存储器。
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4.发明授权公开(公告)号：US06985972B2
公开(公告)日：2006-01-10
申请号：US10264163
申请日：2002-10-03
申请人： James Norris Dieffenderfer , Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Barry Joe Wolford
发明人： James Norris Dieffenderfer , Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Barry Joe Wolford
CPC分类号： G06F13/366 , G06F12/0831 , G06F2212/1028 , G06F2213/0038 , Y02D10/13 , Y02D10/14
摘要： A data processing system with a snooper that is capable of dynamically enabling and disabling its snooping capabilities (i.e., snoop detect and response). The snooper is connected to a bus controller via a plurality of interconnects, including a snooperPresent signal, a snoop response signal and a snoop detect signal. When the snooperPresent signal is asserted, subsequent snoop requests are sent to the snooper, and the snooper is polled for a snoop response. Each snooper is capable of responding at different times (i.e., each snooper operates with different snoop latencies). The bus controller individually tracks the snoop response received from each snooper with the snooperPresent signal enabled. Whenever the snooper wishes to deactivate its snooping capabilities/operations, the snooper de-asserts the snooperPresent signal. The bus controller recognizes this as an indication that the snooper is unavailable. Thus, when the bus controller broadcasts subsequent snoop requests, the bus controller does not send the snoop request to the snooper.
摘要翻译： 具有能够动态地启用和禁用其窥探能力（即，窥探检测和响应）的窥探者的数据处理系统。 窥探者通过多个互连连接到总线控制器，包括窥探信号，窥探响应信号和窥探检测信号。 当snooperPresent信号被断言时，后续的窥探请求被发送到snooper，并且窥探者被轮询以进行侦听响应。 每个窥探者都能够在不同的时间进行响应（即，每个窥探者使用不同的侦听延迟进行操作）。 总线控制器单独跟踪snooperPresent信号启用时从每个窥探者接收的窥探响应。 只要窥探者希望取消其窥探能力/操作，窥探者将断言snooperPresent信号。 总线控制器将此识别为snooper不可用的指示。 因此，当总线控制器广播后续的窥探请求时，总线控制器不向窥探者发送窥探请求。
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5.发明申请公开(公告)号：US20130117593A1
公开(公告)日：2013-05-09
申请号：US13290250
申请日：2011-11-07
申请人： Prudhvi N. Nooney , Jaya Prakash Subramaniam Ganasan , Joseph L. Van Swearingen , Richard Gerard Hofmann
发明人： Prudhvi N. Nooney , Jaya Prakash Subramaniam Ganasan , Joseph L. Van Swearingen , Richard Gerard Hofmann
IPC分类号： G06F1/32
CPC分类号： G06F1/3237 , G06F1/3253 , Y02D10/128 , Y02D10/151 , Y02D50/20
摘要： A System-on-a-Chip (SoC) comprising a controller, an activity counter, a reference pattern detection logic, a master pattern detection logic, an arbiter, a comparator, a tracker circuit, a delay cell circuit, and a request mask circuit coupled to a bus. The bus is configured to support master control. The controller is configured to cause components to enter a low power state. The activity counter is configured to monitor activity. The detection logics are configured to operate on an activity based clock or always on clock. The arbiter is configured to select an initiator. The comparator is configured to compare the output of the detection logics. The tracker circuit is configured to track selection of components. The delay cell circuit is configured to store output of components. The request mask circuit is configured to prevent request to arbiter or any arbiter selected request made from a previous clock cycle.
摘要翻译： 一种片上系统（SoC），包括控制器，活动计数器，参考模式检测逻辑，主模式检测逻辑，仲裁器，比较器，跟踪器电路，延迟单元电路和请求掩码 电路耦合到总线。 总线配置为支持主控制。 控制器被配置为使组件进入低功率状态。 活动计数器配置为监视活动。 检测逻辑被配置为在基于活动的时钟上操作或者始终处于时钟上。 仲裁器被配置为选择启动器。 比较器配置为比较检测逻辑的输出。 跟踪器电路被配置为跟踪组件的选择。 延迟单元电路被配置为存储组件的输出。 请求屏蔽电路被配置为防止对仲裁器的请求或从先前时钟周期进行的任何仲裁器选择的请求。
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6.发明授权Bus clock frequency scaling for a bus interconnect and related devices, systems, and methods 有权总线互连及相关设备，系统和方法的总线时钟频率缩放公开(公告)号：US09286257B2
公开(公告)日：2016-03-15
申请号：US13015657
申请日：2011-01-28
CPC分类号： G06F13/4022 , G06F1/06 , G06F1/3209 , G06F1/324 , Y02D10/126 , Y02D10/151
摘要： Bus clock frequency scaling for a bus interconnect and related devices, systems, and methods are disclosed. In one embodiment, the bus interconnect comprises an interconnect network configurable to connect a master port(s) to a slave port(s). A bus interconnect clock signal clocks the interconnect network. The controller is configured to receive bandwidth information related to traffic communicated over the master port(s) and the slave port(s). The controller is further configured to scale (e.g., increase or decrease) the frequency of the bus interconnect clock signal if the bandwidth of the master port(s) and/or the slave port(s) meets respective bandwidth condition(s), and/or if the latency of the master port(s) meets a respective latency condition(s) for the master port(s). The master port(s) and/or slave port(s) can also be reconfigured in response to a change in frequency of the bus interconnect clock signal to optimize performance and conserve power.
摘要翻译： 公布了总线互连及相关设备，系统和方法的总线时钟频率缩放。 在一个实施例中，总线互连包括可配置为将主端口连接到从端口的互连网络。 总线互连时钟信号对互连网络进行时钟。 控制器被配置为接收与通过主端口和从端口传送的业务相关的带宽信息。 如果主端口和/或从端口的带宽满足相应的带宽条件，则控制器进一步被配置为扩展（例如，增加或减少）总线互连时钟信号的频率，以及 /或如果主端口的延迟满足主端口的相应等待时间条件。 主端口和/或从端口也可以被重新配置以响应总线互连时钟信号的频率变化，以优化性能并节省功率。
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公开(公告)号：US09026744B2
公开(公告)日：2015-05-05
申请号：US11253307
申请日：2005-10-19
申请人： Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Jaya Prakash Subramaniam Ganasan , James Norris Dieffenderfer , James Edward Sullivan
发明人： Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Jaya Prakash Subramaniam Ganasan , James Norris Dieffenderfer , James Edward Sullivan
CPC分类号： G06F13/1621
摘要： The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.
摘要翻译： 本公开涉及一种用于在弱有序处理系统中强制执行强有序存储器访问请求的弱有序处理系统和方法。 处理系统包括多个存储器件和多个处理器。 每个处理器被配置为生成对一个或多个存储器设备的存储器访问请求，其中每个存储器访问请求具有可以被断言以指示强有序请求的属性。 处理系统还包括被配置为将处理器与存储器设备接口的总线互连，总线互连还被配置为基于属性来强制对存储器访问请求的排序限制。
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公开(公告)号：US20100005208A1
公开(公告)日：2010-01-07
申请号：US12561381
申请日：2009-09-17
IPC分类号： G06F13/00
CPC分类号： G06F13/1621 , G06F9/52 , G06F9/522
摘要： The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being produced before the execution of all memory access requests issued by the master device to the memory before the memory barrier.
摘要翻译： 本公开涉及一种弱有序处理系统和在弱有序处理系统中执行存储障碍的方法。 处理系统包括存储器和被配置为向存储器发出存储器访问请求（包括存储器障碍）的主设备。 处理系统还包括被配置为提供主设备对存储器的访问的从设备，从设备还被配置为产生指示由主设备发布的存储器障碍施加的排序约束将被强制的信号，信号 在执行由主设备发出的所有存储器访问请求之前在存储器屏障之前被产生到存储器。
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9.发明授权System and method for providing improved bus utilization via target directed completion 失效通过目标定向完成提供改进的总线利用率的系统和方法公开(公告)号：US06973520B2
公开(公告)日：2005-12-06
申请号：US10195172
申请日：2002-07-11
申请人： Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Richard Nicholas Iachetta, Jr. , Barry Joe Wolford
发明人： Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Richard Nicholas Iachetta, Jr. , Barry Joe Wolford
IPC分类号： G06F13/00 , G06F13/14 , G06F13/364
CPC分类号： G06F13/364
摘要： An electronic system is disclosed, including multiple initiators and one or more targets coupled to a bus, and a request mask control unit (RMCU). The initiators are configured to initiate requests (e.g., read requests and write requests) via the bus, and the targets are configured to receive requests from the initiators via the bus. The targets are also configured to produce multiple MaskEnable signals, wherein each of the MaskEnable signals is generated following an initial request received via the bus, and dependent on a corresponding “masking situation” within the target. The RMCU receives the MaskEnable signals and produces multiple RequestMask signals dependent upon the MaskEnable signals. One or more of the initiators are permitted to repeat requests via the bus dependent upon one or more of the RequestMask signals. This mechanism provides additional bus bandwidth for carrying out successful data transfers.
摘要翻译： 公开了一种电子系统，包括多个启动器和耦合到总线的一个或多个目标，以及请求掩码控制单元（RMCU）。 启动器被配置为经由总线发起请求（例如，读请求和写请求），并且目标被配置为经由总线接收来自发起者的请求。 目标还被配置为产生多个MaskEnable信号，其中每个MaskEnable信号是在经由总线接收到的初始请求之后生成的，并且取决于目标内相应的“屏蔽情况”。 RMCU接收MaskEnable信号，并根据MaskEnable信号产生多个RequestMask信号。 一个或多个启动器被允许经由总线重复请求，取决于一个或多个请求掩码信号。 该机制为进行成功的数据传输提供了额外的总线带宽。
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10.发明申请Method and Apparatus for Adaptive Hysteresis Timer Adjustments for Clock Gating 审中-公开用于时钟门控的自适应滞后定时器调整方法和装置公开(公告)号：US20130064337A1
公开(公告)日：2013-03-14
申请号：US13229943
申请日：2011-09-12
IPC分类号： H04L7/00
CPC分类号： G06F1/08 , G06F1/3237 , G06F1/3253 , Y02D10/128 , Y02D10/151
摘要： Apparatus and method for adaptive hysteresis timer adjustments for clock gating are disclosed. An apparatus comprises a transaction circuit configured to perform transactions. The apparatus further comprises a hysteresis timer having a hysteresis value and configured to start counting based on the hysteresis value when a transaction in the transaction circuit has been completed. The apparatus further comprises a hysteresis timer update circuit configured to monitor the hysteresis timer and the transaction circuit, store an adjustment state based on whether a new transaction is received before, coincident with or after the count of the hysteresis timer expires and adjust the hysteresis value based on the adjustment state.
摘要翻译： 公开了用于时钟门控的自适应滞后定时器调整的装置和方法。 一种装置包括被配置为执行交易的交易电路。 该装置还包括具有迟滞值的滞后定时器，并且被配置为当交易电路中的交易已经完成时基于迟滞值开始计数。 该装置还包括滞后定时器更新电路，其被配置为监视滞后定时器和事务电路，基于在迟滞计时器的计数到期之前是否接收到新的事务，并且调整滞后值来调整调整状态 基于调整状态。
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