公开(公告)号：US08339883B2

公开(公告)日：2012-12-25

申请号：US12948302

申请日：2010-11-17

申请人： Je-min Yu ,  Byung-chul Kim ,  Jun-hyung Kim ,  Sang-joon Hwang

发明人： Je-min Yu ,  Byung-chul Kim ,  Jun-hyung Kim ,  Sang-joon Hwang

IPC分类号： G11C7/00

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002

摘要： A semiconductor memory device includes a bitline sensing amp detecting and amplifying data of a pair of bitlines from a memory cell, a column selecting unit transmitting the data of the pair of bitlines to a pair of local datalines in response to a column selecting signal, a dataline precharging unit precharging the pair of local datalines to a precharging voltage level in response to a precharging signal, and a dataline sensing amp detecting and amplifying data transmitted to the pair of local datalines. The dataline sensing amp includes a charge sync unit discharging the pair of local datalines at the precharging voltage level in response to a first dataline sensing enabling signal and data of the pair of local datalines, and a data sensing unit transmitting data of the pair of local datalines to a pair of global datalines in response to a second dataline sensing enabling signal.

摘要翻译： 半导体存储器件包括：位线检测放大器，用于检测和放大来自存储器单元的一对位线的数据;列选择单元，响应于列选择信号，将一对位线的数据传输到一对本地数据; 数据预充电单元响应于预充电信号将一对本地数据线预充电到预充电电压电平，以及数据感测放大器检测和放大传输到该对本地数据线的数据。 数据传感放大器包括电荷同步单元，响应于第一数据感测使能信号和一对本地数据的数据，以预充电电压电平放电该对本地数据线;以及数据感测单元，传输该对本地数据 响应于第二数据感测使能信号将数据传送到一对全局数据。

公开(公告)号：US20110116334A1

公开(公告)日：2011-05-19

申请号：US12948302

申请日：2010-11-17

申请人： Je-min YU ,  Byung-chul Kim ,  Jun-hyung Kim ,  Sang-joon Hwang

发明人： Je-min YU ,  Byung-chul Kim ,  Jun-hyung Kim ,  Sang-joon Hwang

IPC分类号： G11C7/12 ,  G11C7/08

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002

摘要： A semiconductor memory device includes a bitline sensing amp detecting and amplifying data of a pair of bitlines from a memory cell, a column selecting unit transmitting the data of the pair of bitlines to a pair of local datalines in response to a column selecting signal, a dataline precharging unit precharging the pair of local datalines to a precharging voltage level in response to a precharging signal, and a dataline sensing amp detecting and amplifying data transmitted to the pair of local datalines. The dataline sensing amp includes a charge sync unit discharging the pair of local datalines at the precharging voltage level in response to a first dataline sensing enabling signal and data of the pair of local datalines, and a data sensing unit transmitting data of the pair of local datalines to a pair of global datalines in response to a second dataline sensing enabling signal.

摘要翻译： 半导体存储器件包括：位线检测放大器，用于检测和放大来自存储器单元的一对位线的数据;列选择单元，响应于列选择信号，将一对位线的数据传输到一对本地数据; 数据预充电单元响应于预充电信号将一对本地数据线预充电到预充电电压电平，以及数据感测放大器检测和放大传输到该对本地数据线的数据。 数据传感放大器包括电荷同步单元，响应于第一数据感测使能信号和一对本地数据的数据，以预充电电压电平放电该对本地数据线;以及数据感测单元，传输该对本地数据 响应于第二数据感测使能信号将数据传送到一对全局数据。

公开(公告)号：US20050152209A1

公开(公告)日：2005-07-14

申请号：US11011549

申请日：2004-12-14

申请人： Won-hwa Shin ,  Seong-jin Jang ,  Sang-joon Hwang

发明人： Won-hwa Shin ,  Seong-jin Jang ,  Sang-joon Hwang

IPC分类号： G11C7/10 ,  G11C8/00 ,  G11C11/4093

CPC分类号： G11C7/1078 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/109 ,  G11C11/4093

摘要： A synchronous semiconductor memory device includes a data input buffer and a data strobe input buffer. The data strobe input buffer includes an input buffer circuit and a detection circuit. The input buffer circuit is configured to be enabled based on an active signal, and to compare a data strobe signal with a first reference voltage to generate an internal data strobe signal. The detection circuit is configured to be enabled based on the active signal, and to compare the data strobe signal with a second reference voltage to generate a detection signal for enabling the data input buffer.

摘要翻译： 同步半导体存储器件包括数据输入缓冲器和数据选通输入缓冲器。 数据选通输入缓冲器包括输入缓冲电路和检测电路。 输入缓冲器电路被配置为基于有效信号使能，并且将数据选通信号与第一参考电压进行比较以产生内部数据选通信号。 检测电路被配置为基于有效信号使能，并且将数据选通信号与第二参考电压进行比较，以产生用于启用数据输入缓冲器的检测信号。

公开(公告)号：US07020031B2

公开(公告)日：2006-03-28

申请号：US11011549

申请日：2004-12-14

申请人： Won-hwa Shin ,  Seong-jin Jang ,  Sang-joon Hwang

发明人： Won-hwa Shin ,  Seong-jin Jang ,  Sang-joon Hwang

IPC分类号： G11C7/00

CPC分类号： G11C7/1078 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/109 ,  G11C11/4093

摘要： A synchronous semiconductor memory device includes a data input buffer and a data strobe input buffer. The data strobe input buffer includes an input buffer circuit and a detection circuit. The input buffer circuit is configured to be enabled based on an active signal, and to compare a data strobe signal with a first reference voltage to generate an internal data strobe signal. The detection circuit is configured to be enabled based on the active signal, and to compare the data strobe signal with a second reference voltage to generate a detection signal for enabling the data input buffer.

摘要翻译： 同步半导体存储器件包括数据输入缓冲器和数据选通输入缓冲器。 数据选通输入缓冲器包括输入缓冲电路和检测电路。 输入缓冲器电路被配置为基于有效信号使能，并且将数据选通信号与第一参考电压进行比较以产生内部数据选通信号。 检测电路被配置为基于有效信号使能，并且将数据选通信号与第二参考电压进行比较，以产生用于启用数据输入缓冲器的检测信号。

公开(公告)号：US08379476B2

公开(公告)日：2013-02-19

申请号：US12984342

申请日：2011-01-04

申请人： Beom-seop Lee ,  Young-hyun Jun ,  Sang-joon Hwang

发明人： Beom-seop Lee ,  Young-hyun Jun ,  Sang-joon Hwang

IPC分类号： G11C8/00 ,  G11C5/14 ,  G11C7/00

CPC分类号： G11C7/02 ,  G11C7/222 ,  G11C8/08 ,  G11C8/14 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4099 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10897

摘要： A semiconductor memory device for reducing ripple noise of a back-bias voltage, and a method of driving the semiconductor memory device include a word line driving circuit and a delay logic circuit. The word line driving circuit enables a sub-word line connected to a selected memory cell to a first voltage, and disables the sub-word line of a non-selected memory cell to a second voltage and a third voltage, in response to a sub-word line enable signal, a first word line driving signal, and a second word line driving signal. The delay logic circuit controls the semiconductor memory device so that an amount of charge of the sub-word line that is introduced to the third voltage is greater than an amount of charge of the sub-word line that is introduced to the second voltage by changing a transition point of time of the sub-word line enable signal with respect to a transition point of time of the first word line driving signal, during the disabling of the sub-word line.

摘要翻译： 一种用于减小背偏电压的纹波噪声的半导体存储器件，以及驱动该半导体存储器件的方法包括字线驱动电路和延迟逻辑电路。 字线驱动电路使得连接到所选择的存储单元的子字线成为第一电压，并且响应于子级驱动电路将子选择的非选择存储单元的子字线禁止为第二电压和第三电压 第一字线驱动信号和第二字线驱动信号。 延迟逻辑电路控制半导体存储器件，使得被引入到第三电压的子字线的电荷量大于通过改变引入到第二电压的子字线的电荷量 在子字线禁用期间相对于第一字线驱动信号的转变点的子字线使能信号的转变时间点。

公开(公告)号：US06259642B1

公开(公告)日：2001-07-10

申请号：US09553514

申请日：2000-04-20

申请人： Sang-joon Hwang ,  Ho-cheol Lee

发明人： Sang-joon Hwang ,  Ho-cheol Lee

IPC分类号： G11C702

CPC分类号： G11C7/18 ,  G11C8/08 ,  G11C8/12

摘要： A semiconductor memory device having reduced sensing noise and sensing current by reducing the number of cells activated by a word line is provided. The semiconductor memory device includes a memory cell array, which is segmented into a plurality of memory cell groups in a column direction, and a plurality of sub-word line drivers for selectively activating the sub-word line of a corresponding memory cell group in response to a group selection signal. The semiconductor memory device prevents sensing operation from occurring in a memory cell group which is not selected, while sensing operation is performed in a memory cell group which is selected by the group selection signal.

摘要翻译： 提供了通过减少由字线激活的单元的数量而具有降低的感测噪声和感测电流的半导体存储器件。 半导体存储器件包括在列方向上被分割为多个存储单元组的存储单元阵列和用于响应地选择性地激活对应的存储单元组的子字线的多个子字线驱动器 到组选择信号。 半导体存储器件防止在由组选择信号选择的存储单元组中执行感测操作时在未选择的存储单元组中发生感测操作。

公开(公告)号：US6020761A

公开(公告)日：2000-02-01

申请号：US088135

申请日：1998-06-01

申请人： Sang-joon Hwang ,  Kyung-woo Kang

发明人： Sang-joon Hwang ,  Kyung-woo Kang

IPC分类号： G11C11/417 ,  G11C7/00 ,  G11C11/407 ,  G11C11/409 ,  H03K19/0175 ,  H03K19/0185

CPC分类号： H03K19/018528

摘要： An input buffer that can operate with Low Voltage Transistor-Transistor Logic (LVTTL) and with Stub Series Terminated transceiver Logic (SSTL) includes a differential amplifier that differentially amplifies a reference voltage and an external input signal. A switching system is coupled to the differential amplifier, to supply an external power supply voltage to the differential amplifier under SSTL operating conditions and to supply an internal power supply voltage to the differential amplifier under LVTTL operating conditions. An internal power supply voltage generator is responsive to the external power supply voltage, to generate the internal power supply voltage therefrom. The internal power supply voltage generator supplies the internal power supply voltage to the switching system. The switching system preferably includes a first switch that supplies the external power supply voltage to the differential amplifier in response to an SSTL control signal. A second switch supplies the internal power supply voltage to the differential amplifier in response to an LVTTL control signal.

摘要翻译： 可以使用低压晶体管 - 晶体管逻辑（LVTTL）和Stub系列终端收发器逻辑（SSTL）进行操作的输入缓冲器包括差分放大器，差分放大参考电压和外部输入信号。 开关系统耦合到差分放大器，以在SSTL工作条件下向差分放大器提供外部电源电压，并在LVTTL工作条件下向差分放大器提供内部电源电压。 内部电源电压发生器响应外部电源电压从其产生内部电源电压。 内部电源电压发生器将内部电源电压提供给开关系统。 开关系统优选地包括响应于SSTL控制信号将外部电源电压提供给差分放大器的第一开关。 第二开关响应于LVTTL控制信号而将内部电源电压提供给差分放大器。

公开(公告)号：US20110176375A1

公开(公告)日：2011-07-21

申请号：US12984342

申请日：2011-01-04

申请人： Beom-seop Lee ,  Young-hyun Jun ,  Sang-joon Hwang

发明人： Beom-seop Lee ,  Young-hyun Jun ,  Sang-joon Hwang

IPC分类号： G11C7/00 ,  G11C8/08

CPC分类号： G11C7/02 ,  G11C7/222 ,  G11C8/08 ,  G11C8/14 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4099 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10897

摘要： A semiconductor memory device for reducing ripple noise of a back-bias voltage, and a method of driving the semiconductor memory device include a word line driving circuit and a delay logic circuit. The word line driving circuit enables a sub-word line connected to a selected memory cell to a first voltage, and disables the sub-word line of a non-selected memory cell to a second voltage and a third voltage, in response to a sub-word line enable signal, a first word line driving signal, and a second word line driving signal. The delay logic circuit controls the semiconductor memory device so that an amount of charge of the sub-word line that is introduced to the third voltage is greater than an amount of charge of the sub-word line that is introduced to the second voltage by changing a transition point of time of the sub-word line enable signal with respect to a transition point of time of the first word line driving signal, during the disabling of the sub-word line.

摘要翻译： 一种用于减小背偏电压的纹波噪声的半导体存储器件，以及驱动该半导体存储器件的方法包括字线驱动电路和延迟逻辑电路。 字线驱动电路使得连接到所选择的存储单元的子字线成为第一电压，并且响应于子级驱动电路将子选择的非选择存储单元的子字线禁止为第二电压和第三电压 第一字线驱动信号和第二字线驱动信号。 延迟逻辑电路控制半导体存储器件，使得被引入到第三电压的子字线的电荷量大于通过改变引入到第二电压的子字线的电荷量 在子字线禁用期间相对于第一字线驱动信号的转变点的子字线使能信号的转变时间点。