公开(公告)号：US08450168B2

公开(公告)日：2013-05-28

申请号：US12823728

申请日：2010-06-25

申请人： Jeffrey P. Gambino ,  Matthew D. Moon ,  William J. Murphy ,  James S. Nakos ,  Paul W. Pastel ,  Brett A. Philips

发明人： Jeffrey P. Gambino ,  Matthew D. Moon ,  William J. Murphy ,  James S. Nakos ,  Paul W. Pastel ,  Brett A. Philips

IPC分类号： H01L21/8238 ,  H01L29/76

CPC分类号： H01L28/55 ,  H01L27/11507

摘要： Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator layer of a CMOS structure. The method further includes forming a top plate and a bottom plate over the barrier layer. The method further includes forming a ferro-electric material between the top plate and the bottom plate. The method further includes encapsulating the barrier layer, top plate, bottom plate and ferro-electric material with an encapsulating material. The method further includes forming contacts to the top plate and bottom plate, through the encapsulating material. At least the contact to the top plate and a contact to a diffusion of the CMOS structure are in electrical connection through a common wire.

摘要翻译： 铁电电容器模块，制造方法和设计结构。 制造铁电电容器的方法包括在CMOS结构的绝缘体层上形成阻挡层。 该方法还包括在阻挡层上形成顶板和底板。 该方法还包括在顶板和底板之间形成铁电材料。 该方法还包括用封装材料封装阻挡层，顶板，底板和铁电材料。 该方法还包括通过封装材料形成与顶板和底板的接触。 至少与顶板的接触和与CMOS结构的扩散的接触通过公共导线电连接。

公开(公告)号：US08604618B2

公开(公告)日：2013-12-10

申请号：US13239533

申请日：2011-09-22

申请人： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Xiao Hu Liu ,  Thomas L. McDevitt ,  Gary L. Milo ,  William J. Murphy

发明人： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Xiao Hu Liu ,  Thomas L. McDevitt ,  Gary L. Milo ,  William J. Murphy

IPC分类号： H01L23/485 ,  H01L21/3205

CPC分类号： H01L21/76802 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers.

摘要翻译： 半导体器件及其制造方法包括在绝缘体上的垂直堆叠的层。 每个层包括第一介电绝缘体部分，嵌入在第一介电绝缘体部分内的第一金属导体，覆盖第一金属导体的第一氮化物帽，第二电介质绝缘体部分，嵌入在第二介电绝缘体部分内的第二金属导体 以及覆盖所述第二金属导体的第二氮化物帽。 第一和第二金属导体形成第一垂直堆叠的导体层和第二垂直堆叠的导体层。 第一垂直堆叠的导体层靠近第二垂直堆叠的导体层，并且至少一个气隙位于第一垂直堆叠的导体层和第二垂直堆叠的导体层之间。 上半导体层覆盖第一垂直堆叠的导体层，气隙和第二多个垂直堆叠的导体层。

公开(公告)号：US20130075913A1

公开(公告)日：2013-03-28

申请号：US13239533

申请日：2011-09-22

申请人： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Xiao Hu Liu ,  Thomas L. McDevitt ,  Gary L. Milo ,  William J. Murphy

发明人： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Xiao Hu Liu ,  Thomas L. McDevitt ,  Gary L. Milo ,  William J. Murphy

IPC分类号： H01L23/485 ,  H01L21/3205

CPC分类号： H01L21/76802 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers.

公开(公告)号：US20080173976A1

公开(公告)日：2008-07-24

申请号：US11626548

申请日：2007-01-24

申请人： Anthony K. Stamper ,  Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  William J. Murphy ,  Kunal Vaed

发明人： Anthony K. Stamper ,  Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  William J. Murphy ,  Kunal Vaed

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L27/0688 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/53295 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line (“FEOL”) devices are formed in a semiconductor region of the microelectronic chip, and a plurality of stacked interlevel dielectric (“ILD”) layers are formed to overlie the plurality of FEOL devices, the plurality of stacked ILD layers including a first ILD layer and a second ILD layer, where the second ILD layer is resistant to attack by a first etchant which attacks the first ILD layer. A passive device is formed to overlie at least the first ILD layer. Using the first etchant, a portion of the first ILD layer in registration with the passive device is removed to form an air gap which underlies the passive device in registration with the passive device.

摘要翻译： 提供了一种用于制造微电子芯片的方法，该微电子芯片包括覆盖气隙的诸如电感器的无源器件。 在这种方法中，在微电子芯片的半导体区域中形成多个前端（“FEOL”）器件，并且形成多个层叠的层间电介质（“ILD”）层以覆盖多个 的多个层叠的ILD层，包括第一ILD层和第二ILD层，其中第二ILD层抵抗攻击第一ILD层的第一蚀刻剂的侵袭。 形成无源器件至少覆盖第一ILD层。 使用第一蚀刻剂，除去与无源器件对准的第一ILD层的一部分，以形成与被动器件对准的无源器件下方的气隙。

公开(公告)号：US07662722B2

公开(公告)日：2010-02-16

申请号：US11626548

申请日：2007-01-24

申请人： Anthony K. Stamper ,  Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  William J. Murphy ,  Kunal Vaed

发明人： Anthony K. Stamper ,  Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  William J. Murphy ,  Kunal Vaed

IPC分类号： H01L21/302

CPC分类号： H01L27/0688 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/53295 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line (“FEOL”) devices are formed in a semiconductor region of the microelectronic chip, and a plurality of stacked interlevel dielectric (“ILD”) layers are formed to overlie the plurality of FEOL devices, the plurality of stacked ILD layers including a first ILD layer and a second ILD layer, where the second ILD layer is resistant to attack by a first etchant which attacks the first ILD layer. A passive device is formed to overlie at least the first ILD layer. Using the first etchant, a portion of the first ILD layer in registration with the passive device is removed to form an air gap which underlies the passive device in registration with the passive device.

摘要翻译： 提供了一种用于制造微电子芯片的方法，该微电子芯片包括覆盖气隙的诸如电感器的无源器件。 在这种方法中，在微电子芯片的半导体区域中形成多个前端（“FEOL”）器件，并且形成多个层叠的层间电介质（“ILD”）层以覆盖多个 的多个层叠的ILD层，包括第一ILD层和第二ILD层，其中第二ILD层抵抗攻击第一ILD层的第一蚀刻剂的侵袭。 形成无源器件至少覆盖第一ILD层。 使用第一蚀刻剂，除去与无源器件对准的第一ILD层的一部分，以形成与被动器件对准的无源器件下方的气隙。

公开(公告)号：US09058455B2

公开(公告)日：2015-06-16

申请号：US13354705

申请日：2012-01-20

申请人： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

发明人： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

IPC分类号： G06F17/50 ,  H01L21/768 ,  H01L23/48 ,  H03H9/64 ,  H01L23/00 ,  H01L27/06 ,  H01L49/02 ,  H01L23/66 ,  H01L25/16

CPC分类号： H01L41/293 ,  G06F17/5063 ,  G06F17/5068 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L25/16 ,  H01L27/0694 ,  H01L28/40 ,  H01L41/0815 ,  H01L41/25 ,  H01L2224/03009 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/24145 ,  H01L2225/06548 ,  H03H9/64

摘要： A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

摘要翻译： 在半导体衬底的背面上的集成射频（RF）滤波器的设计结构包括：在衬底的第一侧上的器件; 在衬底的背面上的射频（RF）滤波器; 以及至少一个衬底导体，其从所述衬底的前侧延伸到所述衬底的所述背面并将所述RF滤波器电耦合到所述器件。

公开(公告)号：US08946013B2

公开(公告)日：2015-02-03

申请号：US13364663

申请日：2012-02-02

申请人： Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Xuefeng Liu ,  Benjamin T. Voegeli ,  Steven H. Voldman ,  Michael J. Zierak

发明人： Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Xuefeng Liu ,  Benjamin T. Voegeli ,  Steven H. Voldman ,  Michael J. Zierak

IPC分类号： H01L21/00 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L21/26586 ,  H01L21/26513 ,  H01L29/1045 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.

摘要翻译： 形成从栅电极的边缘排列的一次性结构和与一次性结构对准的漏区。 因此，漏极区域与栅电极的边缘自对准。 一次性结构可以是一次性间隔件，或者替代地，一次性结构可以与栅电极同时形成并且包括与栅电极相同的材料。 在形成漏极区域之后，一次性结构被去除。 漏极区域到栅电极的边缘的自对准提供了与光刻工艺的任何叠加变化无关的基本恒定的漂移距离。

公开(公告)号：US08927869B2

公开(公告)日：2015-01-06

申请号：US13444343

申请日：2012-04-11

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H05K1/00

CPC分类号： H01L24/05 ,  H01B3/306 ,  H01B3/307 ,  H01L21/02118 ,  H01L21/76877 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/48

摘要： Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer.

摘要翻译： 公开了使用有机绝缘材料的引线键合半导体结构和制造方法。 该方法包括在有机绝缘体层中形成金属布线层。 该方法还包括在有机绝缘体层上形成保护层。 该方法还包括在金属布线层上的有机绝缘体层中形成通孔。 该方法还包括在通孔中和保护层上沉积金属层。 该方法还包括用对有机绝缘体层有害的蚀刻化学物图案化金属层。

公开(公告)号：US08766439B2

公开(公告)日：2014-07-01

申请号：US12634741

申请日：2009-12-10

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L23/12

CPC分类号： H01L24/11 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13618 ,  H01L2224/1362 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/1601 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2224/13099 ,  H01L2924/00012

摘要： Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a three-dimensional geometric shape (e.g., a pyramid or cone shape) with a base adjacent to the surface of the chip, a vertex opposite the base and, optionally, mushroom-shaped cap atop the vertex. Each pad can include a single layer of conductive material or multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). The pads can be left exposed to allow for subsequent connection to corresponding solder bumps on a chip carrier or a second chip. Alternatively, solder balls can be positioned on the conductive pads to allow for subsequent connection to corresponding solder-paste filled openings on a chip carrier or a second chip.

摘要翻译： 公开了一种用改进的导电焊盘形成芯片的芯片和方法，其允许与芯片载体或另一个集成电路芯片的柔性C4连接。 垫具有三维几何形状（例如，金字塔或锥形），其具有与芯片表面相邻的基部，与基部相对的顶点以及可选地在顶点顶部的蘑菇形帽。 每个焊盘可以包括单层导电材料或多层导电材料（例如，堆叠在非润湿层上方的润湿层）。 焊盘可以被暴露以允许随后连接到芯片载体或第二芯片上的相应焊料凸块。 或者，焊球可以定位在导电焊盘上，以允许随后连接到芯片载体或第二芯片上相应的焊膏填充的开口。

公开(公告)号：US08765595B2

公开(公告)日：2014-07-01

申请号：US13345120

申请日：2012-01-06

申请人： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Tom C. Lee ,  Xiao H. Liu

发明人： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Tom C. Lee ,  Xiao H. Liu

IPC分类号： H01L21/4763

CPC分类号： H01L23/5227 ,  H01L21/76883 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53295 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.

摘要翻译： BEOL布线结构的制造方法，BEOL布线结构以及BEOL布线结构的设计结构。 BEOL布线可以通过在电介质层中形成第一布线并在无氧气氛中退火第一布线来制造。 在第一线退火之后，形成与第一线垂直对准的第二线。 形成由诸如聚酰亚胺的有机材料组成的最终钝化层，其覆盖第二线的整个侧壁。