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    Ferro-electric capacitor modules, methods of manufacture and design structures
    1.
    发明授权
    Ferro-electric capacitor modules, methods of manufacture and design structures 有权
    铁电电容器模块，制造方法和设计结构

    公开(公告)号：US08450168B2

    公开(公告)日：2013-05-28

    申请号：US12823728

    申请日：2010-06-25

    申请人： Jeffrey P. Gambino ,  Matthew D. Moon ,  William J. Murphy ,  James S. Nakos ,  Paul W. Pastel ,  Brett A. Philips

    发明人： Jeffrey P. Gambino ,  Matthew D. Moon ,  William J. Murphy ,  James S. Nakos ,  Paul W. Pastel ,  Brett A. Philips

    IPC分类号： H01L21/8238 ,  H01L29/76

    CPC分类号： H01L28/55 ,  H01L27/11507

    摘要： Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator layer of a CMOS structure. The method further includes forming a top plate and a bottom plate over the barrier layer. The method further includes forming a ferro-electric material between the top plate and the bottom plate. The method further includes encapsulating the barrier layer, top plate, bottom plate and ferro-electric material with an encapsulating material. The method further includes forming contacts to the top plate and bottom plate, through the encapsulating material. At least the contact to the top plate and a contact to a diffusion of the CMOS structure are in electrical connection through a common wire.

    摘要翻译： 铁电电容器模块，制造方法和设计结构。 制造铁电电容器的方法包括在CMOS结构的绝缘体层上形成阻挡层。 该方法还包括在阻挡层上形成顶板和底板。 该方法还包括在顶板和底板之间形成铁电材料。 该方法还包括用封装材料封装阻挡层，顶板，底板和铁电材料。 该方法还包括通过封装材料形成与顶板和底板的接触。 至少与顶板的接触和与CMOS结构的扩散的接触通过公共导线电连接。

    Hydrogen barrier liner for ferro-electric random access memory (FRAM) chip
    2.
    发明授权
    Hydrogen barrier liner for ferro-electric random access memory (FRAM) chip 有权
    用于铁电随机存取存储器（FRAM）芯片的阻水衬垫

    公开(公告)号：US08395196B2

    公开(公告)日：2013-03-12

    申请号：US12946915

    申请日：2010-11-16

    申请人： Brian M. Czabaj ,  James V. Hart, III ,  William J. Murphy ,  James S. Nakos

    发明人： Brian M. Czabaj ,  James V. Hart, III ,  William J. Murphy ,  James S. Nakos

    IPC分类号： H01L21/02

    CPC分类号： H01L29/66477 ,  H01L29/6684 ,  H01L29/78391

    摘要： A ferro-electric random access memory (FRAM) chip, including a substrate; a first dielectric layer over the substrate; a gate over the first dielectric layer; a first aluminum oxide layer over the first dielectric layer and the gate; a second dielectric layer over the first aluminum oxide layer; a trench through the second dielectric layer and the first aluminum oxide layer to the gate; a hydrogen barrier liner over the second dielectric layer and lining the trench, and contacting the gate; and a silicon dioxide plug over the hydrogen barrier liner substantially filling the trench.

    摘要翻译： 铁电随机存取存储器（FRAM）芯片，包括衬底; 衬底上的第一电介质层; 第一介电层上的栅极; 在第一介电层和栅极上的第一氧化铝层; 在第一氧化铝层上的第二介电层; 通过第二介电层和第一氧化铝层到沟槽的沟槽; 在所述第二电介质层上方的氢阻挡衬垫，并且衬套所述沟槽，并且与所述栅极接触; 以及基本上填充所述沟槽的氢阻挡衬里上的二氧化硅塞。

    HYDROGEN BARRIER LINER FOR FERRO-ELECTRIC RANDOM ACCESS MEMORY (FRAM) CHIP
    3.
    发明申请
    HYDROGEN BARRIER LINER FOR FERRO-ELECTRIC RANDOM ACCESS MEMORY (FRAM) CHIP 有权
    用于电动随机存取存储器（FRAM）芯片的氢屏障线

    公开(公告)号：US20120119273A1

    公开(公告)日：2012-05-17

    申请号：US12946915

    申请日：2010-11-16

    申请人： Brian M. Czabaj ,  James V. Hart, III ,  William J. Murphy ,  James S. Nakos

    发明人： Brian M. Czabaj ,  James V. Hart, III ,  William J. Murphy ,  James S. Nakos

    IPC分类号： H01L29/772 ,  H01L21/336

    CPC分类号： H01L29/66477 ,  H01L29/6684 ,  H01L29/78391

    摘要： A ferro-electric random access memory (FRAM) chip, including a substrate; a first dielectric layer over the substrate; a gate over the first dielectric layer; a first aluminum oxide layer over the first dielectric layer and the gate; a second dielectric layer over the first aluminum oxide layer; a trench through the second dielectric layer and the first aluminum oxide layer to the gate; a hydrogen barrier liner over the second dielectric layer and lining the trench, and contacting the gate; and a silicon dioxide plug over the hydrogen barrier liner substantially filling the trench.

    摘要翻译： 铁电随机存取存储器（FRAM）芯片，包括衬底; 衬底上的第一电介质层; 第一介电层上的栅极; 在第一介电层和栅极上的第一氧化铝层; 在第一氧化铝层上的第二介电层; 通过第二介电层和第一氧化铝层到沟槽的沟槽; 在所述第二电介质层上方的氢阻挡衬垫，并且衬套所述沟槽，并且与所述栅极接触; 以及基本上填充所述沟槽的氢阻挡衬里上的二氧化硅塞。

    Structure and method for reducing vertical crack propagation
    4.
    发明授权
    Structure and method for reducing vertical crack propagation 有权
    减少垂直裂纹扩展的结构和方法

    公开(公告)号：US08604618B2

    公开(公告)日：2013-12-10

    申请号：US13239533

    申请日：2011-09-22

    申请人： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Xiao Hu Liu ,  Thomas L. McDevitt ,  Gary L. Milo ,  William J. Murphy

    发明人： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Xiao Hu Liu ,  Thomas L. McDevitt ,  Gary L. Milo ,  William J. Murphy

    IPC分类号： H01L23/485 ,  H01L21/3205

    CPC分类号： H01L21/76802 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers.

    摘要翻译： 半导体器件及其制造方法包括在绝缘体上的垂直堆叠的层。 每个层包括第一介电绝缘体部分，嵌入在第一介电绝缘体部分内的第一金属导体，覆盖第一金属导体的第一氮化物帽，第二电介质绝缘体部分，嵌入在第二介电绝缘体部分内的第二金属导体 以及覆盖所述第二金属导体的第二氮化物帽。 第一和第二金属导体形成第一垂直堆叠的导体层和第二垂直堆叠的导体层。 第一垂直堆叠的导体层靠近第二垂直堆叠的导体层，并且至少一个气隙位于第一垂直堆叠的导体层和第二垂直堆叠的导体层之间。 上半导体层覆盖第一垂直堆叠的导体层，气隙和第二多个垂直堆叠的导体层。

    Electrical switching apparatus including a trip coil open circuit test circuit and system including the same
    9.
    发明授权
    Electrical switching apparatus including a trip coil open circuit test circuit and system including the same 有权
    包括跳闸线圈开路测试电路的电气开关装置及包括其的系统

    公开(公告)号：US08436739B2

    公开(公告)日：2013-05-07

    申请号：US12206194

    申请日：2008-09-08

    申请人： Robert T. Elms ,  William J. Murphy

    发明人： Robert T. Elms ,  William J. Murphy

    IPC分类号： G08B21/00

    CPC分类号： G01R31/3272 ,  G01R31/3275

    摘要： A circuit breaker includes separable contacts, an operating mechanism structured to open and close the separable contacts, and a trip circuit including a trip coil and a fault detector. The fault detector energizes the trip coil to cause the operating mechanism to open the separable contacts. A test circuit is structured to test the trip coil and determine an open circuit condition thereof. An annunciation circuit is structured to annunciate the open circuit condition of the trip coil.

    摘要翻译： 断路器包括可分离触点，构造成打开和闭合可分离触点的操作机构，以及包括跳闸线圈和故障检测器的跳闸电路。 故障检测器激励跳闸线圈，使操作机构打开可分离触点。 测试电路被构造成测试跳闸线圈并确定其断路条件。 报警电路被构造成用于通知跳闸线圈的开路状况。

    TRANSISTOR AND METHOD OF FORMING THE TRANSISTOR SO AS TO HAVE REDUCED BASE RESISTANCE
    10.
    发明申请
    TRANSISTOR AND METHOD OF FORMING THE TRANSISTOR SO AS TO HAVE REDUCED BASE RESISTANCE 审中-公开
    晶体管和形成晶体管的方法具有降低的基极电阻

    公开(公告)号：US20120313146A1

    公开(公告)日：2012-12-13

    申请号：US13155730

    申请日：2011-06-08

    申请人： Marc W. Cantell ,  Thai Doan ,  Jessica A. Levy ,  Qizhi Liu ,  William J. Murphy ,  Christa R. Willets

    发明人： Marc W. Cantell ,  Thai Doan ,  Jessica A. Levy ,  Qizhi Liu ,  William J. Murphy ,  Christa R. Willets

    IPC分类号： H01L29/737 ,  H01L21/331 ,  H01L29/73

    CPC分类号： H01L29/66234 ,  H01L21/8222 ,  H01L29/0804 ,  H01L29/0817 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7378

    摘要： Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance Rb. Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.

    摘要翻译： 公开了一种晶体管结构，具有完全硅化的外基，用于降低碱电阻Rb。 具体地说，金属硅化物层覆盖外部基体，包括在T形发射体的上部下方延伸的外部基底部分。 用于确保金属硅化物层覆盖外部基极的这一部分的一个示例性技术需要使发射极的上部逐渐变细。 这种锥形允许在处理期间完全去除发射器上部下方的牺牲层，从而将外部基底暴露在下面，并使硅化物所需的金属层沉积在其上。 例如，可以使用高压溅射技术来沉积该金属层，以确保外部基底的所有暴露表面，甚至覆盖在发射体上部以下的那些。