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公开(公告)号：US5915183A
公开(公告)日：1999-06-22
申请号：US105654
申请日：1998-06-26
IPC分类号： H01L21/28 , H01L21/321 , H01L21/336 , H01L21/768 , H01L29/417
CPC分类号： H01L29/66583 , H01L21/28123 , H01L21/3212 , H01L21/76895 , H01L29/41775 , H01L29/41783 , H01L29/665
摘要： A process for forming raised source/drain junctions using CMP (Chemical Mechanical Polishing) combined with a recess etch of blanket polysilicon. The raised source/drains are defined by gate conductors and by raised STI (Shallow Trench Isolation) which also reduces leakage current through the devices and improves the threshold voltage control. The process uses a salicide gate conductor, and uses conventional polysilicon deposition, CMP, and recess steps to form the raised source/drain junctions, such that it is readily implemented in commercially feasible manufacturing processes.
摘要翻译： 使用CMP（化学机械抛光）与毯式多晶硅的凹陷蚀刻结合形成凸起的源极/漏极结的工艺。 凸起的源极/漏极由栅极导体和凸起的STI（浅沟槽隔离）限定，这也减少了通过器件的泄漏电流并改善了阈值电压控制。 该方法使用硅化物栅极导体，并且使用常规的多晶硅沉积，CMP和凹陷步骤来形成升高的源极/漏极结，使得其在商业上可行的制造工艺中容易地实现。
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公开(公告)号：US07262451B2
公开(公告)日：2007-08-28
申请号：US10541660
申请日：2003-01-08
申请人： Jack A. Mandelman , Jeffrey P. Gambino , Geng Wang
发明人： Jack A. Mandelman , Jeffrey P. Gambino , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L27/10894 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/3081 , H01L27/10864
摘要： Semiconductor devices are fabricated in a strained layer region and strained layer-free region of the same substrate. A first semiconductor device, such as a memory cell, e.g. a deep trench storage cell, is formed in a strained layer-free region of the substrate. A strained layer region is selectively formed in the same substrate. A second semiconductor device (66, 68, 70), such as an FET, e.g. an MOSFET logic device, is formed in the strained layer region.
摘要翻译： 半导体器件制造在同一衬底的应变层区域和无应变层的层中。 第一半导体器件，例如存储器单元，例如 在衬底的无应变层的区域中形成深沟槽存储单元。 在相同的衬底中选择性地形成应变层区域。 第二半导体器件（66,68,70），例如FET，例如， 一个MOSFET逻辑器件，形成在应变层区域中。
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公开(公告)号：US06809372B2
公开(公告)日：2004-10-26
申请号：US09756177
申请日：2001-01-09
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/7883
摘要： A flash memory and a method of forming a flash memory, includes forming a polysilicon wordline on a substrate, the wordline having first and second sidewalls, the first sidewall being tapered, with respect to a surface of the substrate, to have a slope angle and the second sidewall having a slope angle greater than the slope angle of the first sidewall. Thereafter, a polysilicon spacer is formed on the second sidewall while simultaneously removing the polysilicon on the first sidewall. The polysilicon spacer forms a floating gate which is surrounded on a plurality of sides by the second sidewall.
摘要翻译： 闪速存储器和形成闪速存储器的方法包括在衬底上形成多晶硅字线，所述字线具有第一和第二侧壁，所述第一侧壁相对于所述衬底的表面是渐缩的，以具有倾斜角和 所述第二侧壁具有大于所述第一侧壁的倾斜角的倾斜角。 此后，在第二侧壁上形成多晶硅间隔物，同时去除第一侧壁上的多晶硅。 多晶硅间隔物形成浮动栅极，其通过第二侧壁在多个侧面上被包围。
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公开(公告)号：US06674134B2
公开(公告)日：2004-01-06
申请号：US09173430
申请日：1998-10-15
IPC分类号： H01L2976
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/823462
摘要： The present invention provides an integrated circuit which comprises a substrate having a plurality of device regions formed therein, said plurality of device regions being electrically isolated from each other by shallow trench isolation (STI) regions and said plurality of device regions each having opposing edges abutting its corresponding STI region; selected ones of said devices regions having a preselected first device width such that an oxide layer formed thereon includes substantially thicker perimeter regions, along said opposing edges, compared to a thinner central region that does not abut its corresponding STI region; and selected other ones of the device regions having a preselected device width substantially narrower in width than the first device width such that an oxide layer formed thereon includes perimeter regions, along opposing edges, that abut each other over its central region thereby preventing formation of a corresponding thinner central region.
摘要翻译： 本发明提供一种集成电路，其包括其中形成有多个器件区的衬底，所述多个器件区通过浅沟槽隔离（STI）区域彼此电隔离，并且所述多个器件区域各自具有相对的边缘邻接 其对应的STI区域; 所选择的所述器件区域具有预先选择的第一器件宽度，使得形成在其上的氧化物层与不相邻其对应的STI区的较薄的中心区域相比，沿着所述相对的边缘包括基本上较厚的周边区域; 以及选定的其它器件区域具有基本上比第一器件宽度窄的宽度的预选器件宽度，使得形成在其上的氧化物层包括沿相对边缘的周边区域，该周边区域在其中心区域上彼此邻接，从而防止形成 相应较薄的中心区域。
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公开(公告)号：US06501131B1
公开(公告)日：2002-12-31
申请号：US09359291
申请日：1999-07-22
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823807 , H01L29/66492 , H01L29/66537 , H01L29/66583
摘要： The process rules for manufacturing semiconductor devices such as MOSFET's are modified to provide dual work-function doping following the customary gate sidewall oxidation step, greatly reducing thermal budget and boron penetration concerns. The concern of thermal budget is further significantly reduced by a device structure which allows a reduced gap aspect ratio while maintaining low sheet resistance values. A reduced gap aspect ratio also relaxes the need for highly reflowable dielectric materials and also facilitates the use of angled source-drain (S-D) and halo implants. Also provided is a novel structure and process for producing a MOSFET channel, lateral doping profile which suppresses short channel effects while providing low S-D junction capacitance and leakage, as well as immunity to hot-carrier effects. This also affords the potential for reduction in the contact stud-to-gate conductor capacitance, because borderless contacts can be formed with an oxide gate sidewall spacer. As a result, the S-D junctions can be doped independently of the gate conductor doping, more easily allowing a variety of MOSFET structures.
摘要翻译： 制造半导体器件如MOSFET的工艺规则被修改，以提供遵循常规栅极侧壁氧化步骤的双重功能掺杂，大大降低了热预算和硼渗透问题。 通过允许减小的间隙宽高比同时保持低的薄层电阻值的装置结构，热预算的关注进一步显着降低。 减小的间隙宽高比也放松了对高回流电介质材料的需要，并且还有助于使用倾斜的源漏（S-D）和晕轮植入物。 还提供了用于产生MOSFET沟道，横向掺杂分布的新型结构和工艺，其抑制短沟道效应，同时提供低S-D结电容和泄漏，以及对热载流子效应的抗扰性。 这也提供了减小接触柱对栅极导体电容的可能性，因为可以用氧化物栅极侧壁间隔物形成无边界接触。 结果，S-D结可以独立于栅极导体掺杂掺杂，更容易地允许各种MOSFET结构。
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6.发明授权Method of manufacturing a semiconductor device having a shallow trench isolating region 失效制造具有浅沟槽隔离区域的半导体器件的方法公开(公告)号：US06479368B1
公开(公告)日：2002-11-12
申请号：US09033067
申请日：1998-03-02
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method of manufacturing a semiconductor device, in which the depth of a divot in a shallow trench isolation can be decreased. The method comprises forming a trench in a semiconductor substrate, for isolating elements, forming a nitride film on a surface of the trench, depositing mask material on an entire surface of the semiconductor substrate, filling the trench with the mask material, etching the mask material until a surface level of the mask material in the trench falls below the surface of the semiconductor substrate, removing an exposed upper portion of the nitride film on the surface of the trench, removing the mask material from the trench, filling the trench with element-isolating material, thereby forming an element-isolating region, and forming a transistor in an element region isolated from another element region by the element-isolating region.
摘要翻译： 一种制造半导体器件的方法，其中可以减少浅沟槽隔离中的凹陷的深度。 该方法包括在半导体衬底中形成沟槽，用于隔离元件，在沟槽的表面上形成氮化物膜，在半导体衬底的整个表面上沉积掩模材料，用掩模材料填充沟槽，蚀刻掩模材料 直到沟槽中的掩模材料的表面水平落在半导体衬底的表面之下，去除沟槽表面上暴露的氮化物膜的上部，从沟槽中去除掩模材料， 从而形成元件隔离区域，并且通过元件隔离区域在与另一个元件区域隔离的元件区域中形成晶体管。
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7.发明授权Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion 失效用于使用受控栅极耗尽的CMOS器件形成混合高压（HV / LV）晶体管的方法公开(公告)号：US06436749B1
公开(公告)日：2002-08-20
申请号：US09658655
申请日：2000-09-08
申请人： William R. Tonti , Claude L. Bertin , Jeffrey P. Gambino , Russell J. Houghton , Jack A. Mandelman , Wilbur D. Pricer
发明人： William R. Tonti , Claude L. Bertin , Jeffrey P. Gambino , Russell J. Houghton , Jack A. Mandelman , Wilbur D. Pricer
IPC分类号： H01L218238
CPC分类号： H01L27/092 , H01L21/823842
摘要： A method for forming mixed high voltage/low voltage (HV/LV) transistors for CMOS devices is disclosed. In an exemplary embodiment, depletion of the gate conductor is controlled by leaving a fixed region of the gate conductor intrinsic, or lightly doped, thus separating the heavily doped low resistivity portion of the electrode with an intrinsic region by use of a conducting dopant barrier. The barrier is conductive in nature, but acts as a well-controlled diffusion barrier, stopping the “fast” diffusion which normally takes place in polysilicon, and eliminating diffusion between the conductors. Thereby, the device performance may be precisely predicted by carefully controlling the gate conductor thickness.
摘要翻译： 公开了一种用于形成用于CMOS器件的混合高压/低压（HV / LV）晶体管的方法。 在示例性实施例中，通过将栅极导体的固定区域固有或轻掺杂来控制栅极导体的耗尽，从而通过使用导电掺杂剂屏障将本征区域的重掺杂低电阻率部分与本征区域分离。 阻挡层本质上是导电的，但是作为良好控制的扩散屏障，停止通常在多晶硅中发生的“快速”扩散，并消除导体之间的扩散。 因此，可以通过仔细地控制栅极导体厚度来精确地预测器件性能。
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公开(公告)号：US06350653B1
公开(公告)日：2002-02-26
申请号：US09689096
申请日：2000-10-12
IPC分类号： H01L21336
CPC分类号： H01L27/10864 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions and logic devices are formed in silicon-on-insulator (“SOI”) regions and where buried, doped glass is used as a mask to form deep trenches for storage in the bulk region. The resulting structure is also disclosed.
摘要翻译： 提出了一种半导体器件，其涉及一种形成嵌入式DRAM和逻辑器件的方法，其中DRAM器件以块状形成，单晶半导体区域和逻辑器件形成在绝缘体上硅（“SOI”）区域中， 其中掩埋的掺杂玻璃用作掩模以形成用于存储在本体区域中的深沟槽。 还公开了所得到的结构。
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公开(公告)号：US06258689B1
公开(公告)日：2001-07-10
申请号：US09626328
申请日：2000-07-26
申请人： Gary B. Bronner , Jeffrey P. Gambino , Jack A. Mandelman , Rick L. Mohler , Carl Radens , William R. Tonti
发明人： Gary B. Bronner , Jeffrey P. Gambino , Jack A. Mandelman , Rick L. Mohler , Carl Radens , William R. Tonti
IPC分类号： H01L2120
CPC分类号： H01L27/10861 , H01L29/66181
摘要： Trench capacitors are fabricated utilizing a method which results in a metallic nitride as a portion of a node electrode in a lower region of the trench. The metallic nitride-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell layouts and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells having various trench configuration and design.
摘要翻译： 使用导致在沟槽的下部区域中作为节点电极的一部分的金属氮化物的方法来制造沟槽电容器。 与具有类似尺寸的常规沟槽电极相比，含金属氮化物的沟槽电极显示出降低的串联电阻，从而能够减少接地规则存储器单元布局和/或降低的单元访问时间。 本发明的沟槽电容器特别可用作具有各种沟槽结构和设计的DRAM存储单元的组件。
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公开(公告)号：US06252271B1
公开(公告)日：2001-06-26
申请号：US09097515
申请日：1998-06-15
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/7883
摘要： A flash memory and a method of forming a flash memory, includes forming a polysilicon wordline on a substrate, the wordline having first and second sidewalls, the first sidewall being tapered, with respect to a surface of the substrate, to have a slope angle and the second sidewall having a slope angle greater than the slope angle of the first sidewall. Thereafter, a polysilicon spacer is formed on the second sidewall while simultaneously removing the polysilicon on the first sidewall. The polysilicon spacer forms a floating gate which is surrounded on a plurality of sides by the second sidewall.
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