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    Semiconductor devices including line patterns separated by cutting regions
    3.
    发明授权
    Semiconductor devices including line patterns separated by cutting regions 有权
    半导体器件包括由切割区分开的线图案

    公开(公告)号：US07898007B2

    公开(公告)日：2011-03-01

    申请号：US11961551

    申请日：2007-12-20

    申请人： Sung-Bok Lee ,  Joon-Hee Lee

    发明人： Sung-Bok Lee ,  Joon-Hee Lee

    IPC分类号： H01L23/52

    CPC分类号： H01L27/11568 ,  H01L27/0207 ,  H01L27/115

    摘要： Semiconductor devices are provided. A semiconductor device can include a substrate and a plurality of dummy line patterns on the substrate that extend in a first direction parallel with one another. Each of the dummy line patterns can include a plurality of sub-line patterns aligned along the first direction and which are separated from each other by at least one cutting region therebetween. The dummy line patterns can include first and second dummy line patterns which are adjacent to each other in a second direction that is perpendicular to the first direction. At least one of the cutting regions between a pair of sub-line patterns of the first dummy line pattern is aligned with and bounded by one of the sub-line patterns of the second dummy line pattern in the second direction.

    摘要翻译： 提供半导体器件。 半导体器件可以包括衬底和在基板上的彼此平行的第一方向上延伸的多个虚拟线图案。 虚线图案中的每一个可以包括沿着第一方向排列的多个子线图案，并且通过其间的至少一个切割区域彼此分离。 假线图案可以包括在垂直于第一方向的第二方向上彼此相邻的第一和第二假线图案。 第一虚线图案的一对子线图案之间的切割区域中的至少一个与第二虚线图案的第二方向上的一条子线图形对准并限定在第二方向上。

    Non-volatile memory devices having floating gates and related methods of forming the same
    4.
    发明申请
    Non-volatile memory devices having floating gates and related methods of forming the same 失效
    具有浮动栅极的非易失性存储器件及其相关方法

    公开(公告)号：US20070108498A1

    公开(公告)日：2007-05-17

    申请号：US11594327

    申请日：2006-11-08

    申请人： Joon-Hee Lee ,  Jong-Ho Park ,  Jin-Hyun Shin ,  Sung-Hoi Hur ,  Yong-Seok Kim ,  Jong-Won Kim

    发明人： Joon-Hee Lee ,  Jong-Ho Park ,  Jin-Hyun Shin ,  Sung-Hoi Hur ,  Yong-Seok Kim ,  Jong-Won Kim

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

    摘要： A nonvolatile memory device may include a substrate having a cell region, and a cell device isolation layer on the cell region of the substrate to define a cell active region. A floating gate may include a lower floating gate and an upper floating gate sequentially stacked on the cell active region, and a tunnel insulation pattern may be between the floating gate and the cell active region. A control gate electrode may be on the floating gate, and a blocking insulation pattern may be between the control gate electrode and the floating gate. More particularly, the upper floating gate may include a flat portion on the lower floating gate and a pair of wall portions extending upward from both edges of the flat portion adjacent to the cell device isolation layer. Moreover, a width of an upper portion of a space surrounded by the flat portion and the pair of wall portions may be larger than a width of a lower portion of the space. Related methods are also discussed.

    摘要翻译： 非易失性存储器件可以包括具有单元区域的衬底和在衬底的单元区域上的单元器件隔离层，以限定电池活性区域。 浮置栅极可以包括顺序堆叠在单元有源区上的下浮置栅极和上浮置栅极，并且隧道绝缘图案可以在浮栅和电池有源区之间。 控制栅极电极可以在浮置栅极上，并且阻挡绝缘图案可以在控制栅电极和浮栅之间。 更具体地说，上部浮动栅极可以包括在下部浮动栅极上的平坦部分和从邻近电池器件隔离层的平坦部分的两个边缘向上延伸的一对壁部分。 此外，由平坦部分和一对壁部分围绕的空间的上部的宽度可以大于空间的下部的宽度。 还讨论了相关方法。

    Vertical cell-type semiconductor device having protective pattern
    6.
    发明授权
    Vertical cell-type semiconductor device having protective pattern 有权
    具有保护图案的垂直单元型半导体器件

    公开(公告)号：US09281414B2

    公开(公告)日：2016-03-08

    申请号：US14151288

    申请日：2014-01-09

    申请人： Jin-Yeon Won ,  Joon-Hee Lee ,  Seung-Woo Paek ,  Dong-Seog Eun

    发明人： Jin-Yeon Won ,  Joon-Hee Lee ,  Seung-Woo Paek ,  Dong-Seog Eun

    IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/66

    CPC分类号： H01L29/42344 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

    摘要： According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.

    摘要翻译： 根据本发明构思的示例性实施例，半导体器件包括：衬底，以及包括层间绝缘层和交替层叠在衬底上的栅电极的堆叠结构。 堆叠结构在衬底上限定通孔。 栅电极各自包括在通孔和栅电极的第二部分之间的第一部分。 通道图案可以在通孔中。 隧道层可围绕通道图案。 电荷陷阱层可围绕隧道层，并且保护图案可围绕栅电极的第一部分。 保护图案可以在栅电极的第一部分和电荷陷阱层之间。

    Semiconductor memory device having mount test circuits and mount test method thereof
    7.
    发明授权
    Semiconductor memory device having mount test circuits and mount test method thereof 失效
    具有安装测试电路及其安装测试方法的半导体存储器件

    公开(公告)号：US08108741B2

    公开(公告)日：2012-01-31

    申请号：US12219815

    申请日：2008-07-29

    申请人： Byoung-Sul Kim ,  Joon-Hee Lee ,  Kwan-Yong Jin ,  Seung-Hee Lee

    发明人： Byoung-Sul Kim ,  Joon-Hee Lee ,  Kwan-Yong Jin ,  Seung-Hee Lee

    IPC分类号： G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/28 ,  G11C29/40 ,  G11C2029/4002

    摘要： A semiconductor memory device having a mount test circuit and a mount test method thereof are provided. The test circuit for use in a semiconductor memory device including a plurality of memory blocks may include a comparison unit for comparing test data of at least two memory blocks selected from the plurality of memory blocks, deciding whether or not the test data of the selected memory blocks are identical, and outputting a pass signal or fail signal as a flag signal; and an output selection unit for selecting any one of the selected memory blocks as an output memory block, and changing the output memory block whenever the fail signal is generated from the comparison unit, thus forming it as a data output path, which may lessen error occurrence.

    摘要翻译： 提供一种具有安装测试电路及其安装测试方法的半导体存储器件。 用于包括多个存储块的半导体存储器件的测试电路可以包括：比较单元，用于比较从多个存储块中选出的至少两个存储块的测试数据，判断所选择的存储器的测试数据 块相同，并输出通过信号或失败信号作为标志信号; 以及输出选择单元，用于选择所选择的存储器块中的任何一个作为输出存储器块，并且每当从比较单元产生故障信号时改变输出存储器块，从而将其形成为可以减少误差的数据输出路径 发生。

    Semiconductor devices with sidewall conductive patterns and methods of fabricating the same
    8.
    发明授权
    Semiconductor devices with sidewall conductive patterns and methods of fabricating the same 失效
    具有侧壁导电图案的半导体器件及其制造方法

    公开(公告)号：US07973354B2

    公开(公告)日：2011-07-05

    申请号：US12133146

    申请日：2008-06-04

    申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Joon-Hee Lee ,  Hwa-Kyung Shin

    发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Joon-Hee Lee ,  Hwa-Kyung Shin

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11529

    摘要： A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive patter. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.

    摘要翻译： 公开了一种栅极图案，其包括半导体衬底，下导电图案，上导电图案和侧壁导电图案。 下导电图案在基板上。 绝缘图案位于下导电图案上。 上导电图案位于与下导电图案相对的绝缘图案上。 侧壁导电图案位于上导电图案和下导电图案的侧壁的至少一部分上。 侧壁导电图形电连接上导电图案和下导电图案。 下导电图案的上边缘部分可以相对于下导电图案的下边缘部分凹进，以在其上限定凸缘。 侧壁导电图案可以直接在下导电图案的凹陷的上边缘部分的凸缘和侧壁上。

    Semiconductor devices with sidewall conductive patterns methods of fabricating the same
    10.
    发明授权
    Semiconductor devices with sidewall conductive patterns methods of fabricating the same 有权
    具有侧壁导电图案的半导体器件制造方法

    公开(公告)号：US07397093B2

    公开(公告)日：2008-07-08

    申请号：US11241458

    申请日：2005-09-30

    申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Joon-Hee Lee ,  Hwa-Kyung Shin

    发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Joon-Hee Lee ,  Hwa-Kyung Shin

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11529

    摘要： A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.

    摘要翻译： 公开了一种栅极图案，其包括半导体衬底，下导电图案，上导电图案和侧壁导电图案。 下导电图案在基板上。 绝缘图案位于下导电图案上。 上导电图案位于与下导电图案相对的绝缘图案上。 侧壁导电图案位于上导电图案和下导电图案的侧壁的至少一部分上。 侧壁导电图形电连接上导电图案和下导电图案。 下导电图案的上边缘部分可以相对于下导电图案的下边缘部分凹进，以在其上限定凸缘。 侧壁导电图案可以直接在下导电图案的凹陷的上边缘部分的凸缘和侧壁上。