公开(公告)号：US20060119437A1

公开(公告)日：2006-06-08

申请号：US11270957

申请日：2005-11-10

申请人： Axel Thomsen ,  Yunteng Huang ,  Jerrell Hein ,  Derrick Wei

发明人： Axel Thomsen ,  Yunteng Huang ,  Jerrell Hein ,  Derrick Wei

IPC分类号： H03L7/00

CPC分类号： H03L7/0898 ,  H03L1/022 ,  H03L1/026 ,  H03L7/095 ,  H03L7/0992 ,  H03L7/197 ,  H03L7/1976 ,  H03L7/23 ,  H03L7/235 ,  H03L2207/50 ,  H04J3/0688

摘要： A voltage controlled clock synthesizer includes a phase-locked loop (PLL) circuit that receives a timing reference signal, a controllable oscillator circuit, such as a VCO, providing an oscillator output signal, and a feedback divider circuit coupled to the oscillator output signal. The frequency of the oscillator output signal is determined in part according to a stored value used to generate a first digital control signal that determines a divide ratio of the feedback divider circuit. A control voltage present on a voltage control input adjusts the frequency of the oscillator output signal around a frequency determined by the stored value. The control voltage is converted to second digital signal and is utilized in determining the first digital control signal in combination with the stored value.

摘要翻译： 电压控制时钟合成器包括接收定时参考信号的锁相环（PLL）电路，提供振荡器输出信号的可控振荡器电路，例如VCO，以及耦合到振荡器输出信号的反馈分频器电路。 振荡器输出信号的频率部分地根据用于产生确定反馈分频器电路的分频比的第一数字控制信号的存储值来确定。 存在于电压控制输入端的控制电压根据由存储的值确定的频率调整振荡器输出信号的频率。 控制电压被转换为第二数字信号，并用于与所存储的值组合确定第一数字控制信号。

公开(公告)号：US20060119402A1

公开(公告)日：2006-06-08

申请号：US11270954

申请日：2005-11-10

申请人： Axel Thomsen ,  Yunteng Huang ,  Jerrell Hein ,  Michael Petrowski

发明人： Axel Thomsen ,  Yunteng Huang ,  Jerrell Hein ,  Michael Petrowski

IPC分类号： H03B21/00

CPC分类号： H03L7/23 ,  H03L7/0898 ,  H03L7/197 ,  H03L7/1976

摘要： A phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit having an output coupled to the phase detector and an input coupled to the controllable oscillator circuit. The phase-locked loop circuit is coupled to output one of a plurality of output signals having an arbitrary frequency relationship to each other according to a frequency selection mechanism, the frequency selection mechanism including one or more input terminals coupled to control a divide ratio of the feedback divider circuit. The frequency selection mechanism selects one of a plurality of stored values. The selected stored value controls, at least in part, a divide ratio of the feedback divider circuit, thereby providing a pin programmable device capable of selecting among output frequencies having an arbitrary relationship to each other.

摘要翻译： 锁相环（PLL）电路包括用于接收定时参考信号的输入端，耦合以接收定时参考信号的相位检测器电路，根据相位检测器电路的输出控制的可控振荡器电路，以及反馈分配器 电路具有耦合到相位检测器的输出端和耦合到可控振荡器电路的输入端。 锁相环电路根据频率选择机构耦合到输出具有任意频率关系的多个输出信号中的一个，所述频率选择机构包括一个或多个输入端，用于控制所述频率选择机构的分频比 反馈分频电路。 频率选择机构选择多个存储值中的一个。 选择的存储值至少部分地控制反馈分频器电路的分频比，从而提供能够在彼此具有任意关系的输出频率之间进行选择的引脚可编程器件。

公开(公告)号：US20070146083A1

公开(公告)日：2007-06-28

申请号：US11681941

申请日：2007-03-05

申请人： Jerrell Hein ,  Axel Thomsen

发明人： Jerrell Hein ,  Axel Thomsen

IPC分类号： H03L7/00

CPC分类号： H03L1/022 ,  H03L1/026 ,  H03L7/095 ,  H03L7/0992 ,  H03L7/1976 ,  H03L7/235 ,  H03L2207/50

摘要： A clock device having a resonating device such as a crystal of SAW supplying a controllable oscillator such as a digitally controlled oscillator is calibrated by supplying a calibration clock. A phase-locked loop is utilized to generate one or more correction factors causing the PLL to lock to the calibration clock. The one or more correction factors are then stored in non-volatile memory.

摘要翻译： 通过提供校准时钟来校准具有诸如数字控制振荡器等可控振荡器的SAW的晶体谐振装置的时钟装置。 利用锁相环产生一个或多个校正因子，使PLL锁定到校准时钟。 然后将一个或多个校正因子存储在非易失性存储器中。

公开(公告)号：US07187241B2

公开(公告)日：2007-03-06

申请号：US10675543

申请日：2003-09-30

申请人： Jerrell Hein ,  Axel Thomsen

发明人： Jerrell Hein ,  Axel Thomsen

IPC分类号： H03L7/00

CPC分类号： H03L1/022 ,  H03L1/026 ,  H03L7/095 ,  H03L7/0992 ,  H03L7/1976 ,  H03L7/235 ,  H03L2207/50

摘要： A clock device having a resonating device such as a crystal of SAW supplying a controllable oscillator such as a digitally controlled oscillator is calibrated by supplying a calibration clock. A phase-locked loop is utilized to generate one or more correction factors causing the PLL to lock to the calibration clock. The one or more correction factors are then stored in non-volatile memory.

摘要翻译： 通过提供校准时钟来校准具有诸如数字控制振荡器等可控振荡器的SAW的晶体谐振装置的时钟装置。 利用锁相环产生一个或多个校正因子，使PLL锁定到校准时钟。 然后将一个或多个校正因子存储在非易失性存储器中。

公开(公告)号：US20050281403A1

公开(公告)日：2005-12-22

申请号：US11093730

申请日：2005-03-30

申请人： Jerrell Hein ,  Navdeep Sooch

发明人： Jerrell Hein ,  Navdeep Sooch

IPC分类号： H04L25/02 ,  H04M3/00 ,  H04M3/22 ,  H04M19/00 ,  H04Q3/42 ,  H04M1/00 ,  H04M9/00

CPC分类号： H04M19/005 ,  H04M3/005 ,  H04M3/2272

摘要： A subscriber line interface circuit apparatus includes a signal processor having sense inputs for sensed tip and ring signals of a subscriber loop. The signal processor generates linefeed driver control signals in response to the sensed signals. A linefeed driver provides the sensed tip and ring signals. The linefeed driver drives the subscriber loop in accordance with the linefeed driver control signals.

摘要翻译： 用户线接口电路设备包括信号处理器，其具有用于感测到的用户环路的尖端和环形信号的感测输入。 信号处理器响应于感测到的信号而产生线路馈送驱动器控制信号。 换行驱动器提供感测到的尖端和振铃信号。 换行驱动器根据换行驱动器控制信号驱动用户回路。

公开(公告)号：US20070201687A1

公开(公告)日：2007-08-30

申请号：US11676513

申请日：2007-02-20

申请人： Jerrell Hein ,  Navdeep Sooch

发明人： Jerrell Hein ,  Navdeep Sooch

IPC分类号： H04M1/00 ,  H04M9/00

CPC分类号： H04M1/738 ,  H04M1/745 ,  H04M3/005 ,  H04M3/04 ,  H04M3/2272 ,  H04M19/00 ,  H04M19/005

摘要： An integrated circuit having sense inputs for a sensed tip signal and a sensed ring signal of a subscriber loop is disclosed. The integrated circuit processes the sensed signals to generate an analog control signal for a subscriber loop linefeed driver. The linefeed driver does not reside within a same integrated circuit.

摘要翻译： 公开了一种具有感测尖端信号的感测输入和用户环路的感测振铃信号的集成电路。 集成电路处理所感测的信号以产生用于用户环路线路馈送驱动器的模拟控制信号。 换行驱动器不在同一集成电路内。

公开(公告)号：US20050068118A1

公开(公告)日：2005-03-31

申请号：US10675529

申请日：2003-09-30

申请人： Jerrell Hein

发明人： Jerrell Hein

IPC分类号： H03L1/02 ,  H03L7/095 ,  H03L7/099 ,  H03L7/197 ,  H03L7/23 ,  H03B5/32

CPC分类号： H03L7/1976 ,  H03L1/022 ,  H03L1/026 ,  H03L7/095 ,  H03L7/0992 ,  H03L7/235 ,  H03L2207/50

摘要： A device is provided for use in, e.g., XO and VCXO applications that utilizes a terminal that can function in a first mode as a serial communications port and in a second mode as an output enable terminal controlling, for example, the clock output(s). In the first mode, the output enable function is unavailable through the terminal. After the terminal is programmed to operate in the second mode, the terminal functions permanently in the second mode.

摘要翻译： 提供了一种用于例如XO和VCXO应用中的设备，其利用可以在第一模式中工作的终端作为串行通信端口，并且在第二模式中用作控制例如时钟输出的输出使能端 ）。 在第一种模式下，通过终端输出使能功能不可用。 在终端被编程为在第二模式中操作之后，终端在第二模式中永久地运行。

公开(公告)号：US20070201686A1

公开(公告)日：2007-08-30

申请号：US11676929

申请日：2007-02-20

申请人： Jerrell Hein ,  Navdeep Sooch

发明人： Jerrell Hein ,  Navdeep Sooch

IPC分类号： H04M1/00

CPC分类号： H04M1/738 ,  H04M1/745 ,  H04M3/005 ,  H04M3/04 ,  H04M3/2272 ,  H04M19/00 ,  H04M19/005

摘要： An integrated circuit having sense inputs for a sensed tip signal and a sensed ring signal of a subscriber loop is disclosed. The integrated circuit processes the sensed signals to generate a control signal for a subscriber loop linefeed driver.

摘要翻译： 公开了一种具有感测尖端信号的感测输入和用户环路的感测振铃信号的集成电路。 集成电路处理所感测的信号以产生用户回路换行驱动器的控制信号。

公开(公告)号：US20050220291A1

公开(公告)日：2005-10-06

申请号：US11094832

申请日：2005-03-30

申请人： Jerrell Hein ,  Marius Goldenberg

发明人： Jerrell Hein ,  Marius Goldenberg

IPC分类号： H04M1/00 ,  H04M19/00

CPC分类号： H04M19/005

摘要： A subscriber line interface circuit apparatus includes tip/ring sense circuitry generating a tip sense signal and a ring sense signal from three sensed currents, wherein the tip sense signal and the ring sense signal correspond to subscriber loop tip and ring currents, respectively. In one embodiment, the tip/ring sense circuitry includes a current mirror generating first and second mirrored sense currents from a first sense current proportional to a battery feed node voltage of a subscriber loop. Current differencing circuitry provides the tip sense signal from a difference between the first mirrored sense current and a second sense current associated with a tip line of the subscriber loop. The current differencing circuitry provides the ring sense signal from a difference between the second mirrored sense current and a third sense current associated with a ring line of the subscriber loop.

摘要翻译： 用户线路接口电路设备包括尖端/环路感测电路，其产生来自三个感测电流的尖端感测信号和环路感测信号，其中尖端感测信号和环路感测信号分别对应于用户环路尖端和环形电流。 在一个实施例中，尖端/环路感测电路包括电流镜，其从与用户环路的电池馈送节点电压成比例的第一感测电流产生第一和第二镜像检测电流。 电流差分电路从第一镜像检测电流和与用户环路的尖端线相关联的第二感测电流之间的差异提供尖端感测信号。 电流差分电路从第二镜像检测电流和与用户环路的环线相关联的第三检测电流之间的差异提供环形感测信号。

公开(公告)号：US20060294409A1

公开(公告)日：2006-12-28

申请号：US11148995

申请日：2005-06-09

申请人： Jerrell Hein

发明人： Jerrell Hein

IPC分类号： G06F1/00

CPC分类号： G01R31/31922 ,  G01R31/31725 ,  G01R31/31937

摘要： A technique for performing frequency margin testing of communications system circuit boards incorporates a frequency agile clock source on a communications system circuit board. The clock source may be programmed to operate the circuit board at a nominal operating frequency and at frequencies suitable to characterize actual and/or apparent frequency tolerances of the circuit board. The technique maintains transmission line integrity of the on-board clock.

摘要翻译： 用于执行通信系统电路板的频率裕度测试的技术在通信系统电路板上并入频率捷变时钟源。 时钟源可以被编程为以标称工作频率和适合于表征电路板的实际和/或表观频率容限的频率来操作电路板。 该技术保持板载时钟的传输线完整性。