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    Methods for Treating Epithelian Mesenchymal Transition Related Diseases
    3.
    发明申请
    Methods for Treating Epithelian Mesenchymal Transition Related Diseases 审中-公开
    治疗上皮间质转化相关疾病的方法

    公开(公告)号：US20160317548A1

    公开(公告)日：2016-11-03

    申请号：US15144286

    申请日：2016-05-02

    申请人： Bing Tian ,  Allan Brasier

    发明人： Bing Tian ,  Allan Brasier

    IPC分类号： A61K31/551 ,  A61K45/06

    CPC分类号： A61K31/551 ,  A61K45/06 ,  A61K2300/00

    摘要： Certain embodiments are directed to methods of treating chronic lung diseases in a subject comprising administering to a subject diagnosed with, exhibiting symptoms of, or at risk of developing a chronic lung disease a therapeutically effective amount of a BRD4 inhibitor or a CDK9 inhibitor to the subject.

    摘要翻译： 某些实施方案涉及在受试者中治疗慢性肺部疾病的方法，其包括向受试者施用治疗有效量的BRD4抑制剂或CDK9抑制剂的被诊断患有慢性肺部疾病的症状或处于其中的风险的受试者 。

    Methods and apparatuses for automated circuit design
    4.
    发明授权
    Methods and apparatuses for automated circuit design 有权
    自动化电路设计方法和装置

    公开(公告)号：US07620917B2

    公开(公告)日：2009-11-17

    申请号：US10958899

    申请日：2004-10-04

    申请人： Bing Tian ,  Kenneth S. McElvain

    发明人： Bing Tian ,  Kenneth S. McElvain

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5045 ,  G06F17/5077

    摘要： Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a logic function feeding a carry chain is implemented through extending the carry chain and through using the extended portion of the carry chain. In one aspect of an embodiment, control/non-control loads are separated from each other through replicating the driver elements of the mixed control/non-control loads. In one aspect of an embodiment, a read only memory (ROM) is implemented using a random access memory (RAM). In one embodiment, a register at the input side of the ROM is generated through inserting a register that is clocked at an inverted clock signal or through retiming a register from the output side of the ROM.

    摘要翻译： 自动合成电路的方法和装置。 在一个实施例的一个方面，通过延伸进位链和通过使用进位链的延伸部分来实现进给进位链的逻辑功能。 在一个实施例的一个方面，控制/非控制负载通过复制混合控制/非控制负载的驱动元件彼此分离。 在一个实施例的一个方面，使用随机存取存储器（RAM）来实现只读存储器（ROM）。 在一个实施例中，通过插入以反相时钟信号计时的寄存器或通过从ROM的输出侧重新定时寄存器来产生在ROM的输入侧的寄存器。

    Methods and Apparatuses for Automated Circuit Design
    6.
    发明申请
    Methods and Apparatuses for Automated Circuit Design 有权
    自动电路设计的方法与装置

    公开(公告)号：US20100138804A1

    公开(公告)日：2010-06-03

    申请号：US12580796

    申请日：2009-10-16

    申请人： Bing Tian ,  Kenneth S. McElvain

    发明人： Bing Tian ,  Kenneth S. McElvain

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5045 ,  G06F17/5077

    摘要： Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a logic function feeding a carry chain is implemented through extending the carry chain and through using the extended portion of the carry chain. In one aspect of an embodiment, control/non-control loads are separated from each other through replicating the driver elements of the mixed control/non-control loads. In one aspect of an embodiment, a read only memory (ROM) is implemented using a random access memory (RAM). In one embodiment, a register at the input side of the ROM is generated through inserting a register that is clocked at an inverted clock signal or through retiming a register from the output side of the ROM.

    摘要翻译： 自动合成电路的方法和装置。 在一个实施例的一个方面，通过延伸进位链和通过使用进位链的延伸部分来实现进给进位链的逻辑功能。 在一个实施例的一个方面，控制/非控制负载通过复制混合控制/非控制负载的驱动元件彼此分离。 在一个实施例的一个方面，使用随机存取存储器（RAM）来实现只读存储器（ROM）。 在一个实施例中，通过插入以反相时钟信号计时的寄存器或通过从ROM的输出侧重新定时寄存器来产生在ROM的输入侧的寄存器。

    Methods and apparatuses for automated circuit design
    7.
    发明申请
    Methods and apparatuses for automated circuit design 有权

    公开(公告)号：US20060075180A1

    公开(公告)日：2006-04-06

    申请号：US10958899

    申请日：2004-10-04

    申请人： Bing Tian ,  Kenneth McElvain

    发明人： Bing Tian ,  Kenneth McElvain

    IPC分类号： G06F12/02 ,  G06F12/00 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F17/505 ,  G06F17/5045 ,  G06F17/5077

    摘要： Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a logic function feeding a carry chain is implemented through extending the carry chain and through using the extended portion of the carry chain. In one aspect of an embodiment, control/non-control loads are separated from each other through replicating the driver elements of the mixed control/non-control loads. In one aspect of an embodiment, a read only memory (ROM) is implemented using a random access memory (RAM). In one embodiment, a register at the input side of the ROM is generated through inserting a register that is clocked at an inverted clock signal or through retiming a register from the output side of the ROM.

    Methods and apparatuses for reset conditioning in integrated circuits
    8.
    发明授权
    Methods and apparatuses for reset conditioning in integrated circuits 有权
    集成电路中复位调理的方法和装置

    公开(公告)号：US07594211B1

    公开(公告)日：2009-09-22

    申请号：US11601411

    申请日：2006-11-17

    申请人： Bing Tian ,  Kenneth S. McElvain

    发明人： Bing Tian ,  Kenneth S. McElvain

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F1/24

    摘要： Embodiments of the present invention disclose methods and apparatuses to reduce metastability problem related to propagation delay of reset signals in integrated circuits, with preferred applications in automatic physical synthesis for RTL (register transfer level) netlist. In an embodiment, a reset conditioning circuit is inserted into the original integrated circuit to make the reset behavior more reliable to avoid unpredictable states, especially for the de-assertion state of the reset signal. The reset conditioning circuit can provide an asynchronous reset signal output with extended duration so that all the load registers employing asynchronous reset signal will get the reset properly. Further, the reset conditioning circuit can modify the timing of the reset signal so that its de-assertion edge is synchronized with a rising clock edge. In another embodiment, the reset conditioning circuit replicates a synchronous reset signal to provide a reset signal closer to loads or registers at a plurality of circuit modules or partitions. The generation of the reset conditioning circuit is well suitable for physical synthesis of RTL netlists, especially for automatic physical synthesis.

    摘要翻译： 本发明的实施例公开了用于减少与集成电路中的复位信号的传播延迟有关的亚稳态问题的方法和装置，优选应用于RTL（寄存器传送级）网表的自动物理合成。 在一个实施例中，将复位调节电路插入到原始集成电路中，以使复位行为更可靠以避免不可预测的状态，特别是对于复位信号的去断言状态。 复位调理电路可以提供具有延长持续时间的异步复位信号输出，使得采用异步复位信号的所有负载寄存器将正确地复位。 此外，复位调节电路可以修改复位信号的定时，使得其去激活边沿与上升时钟沿同步。 在另一个实施例中，复位调节电路复制同步复位信号以提供更接近多个电路模块或分区处的负载或寄存器的复位信号。 复位调节电路的产生非常适合RTL网表的物理合成，特别是对于自动物理合成。

    Method to improve routability in programmable logic devices via prioritized augmented flows
    9.
    发明授权
    Method to improve routability in programmable logic devices via prioritized augmented flows 有权
    通过优先级增强流程改进可编程逻辑设备中可路由性的方法

    公开(公告)号：US06466050B1

    公开(公告)日：2002-10-15

    申请号：US09894220

    申请日：2001-06-27

    申请人： Haneef D. Mohammed ,  Joseph P. Skudlarek ,  Bing Tian

    发明人： Haneef D. Mohammed ,  Joseph P. Skudlarek ,  Bing Tian

    IPC分类号： H03K19177

    CPC分类号： H03K19/17764 ,  H03K19/17736

    摘要： A method and system for routing signals through interconnect matrices in a programmable logic device such that downstream routing failures can be reduced. In one embodiment, the invention is used to improve routing in complex programmable logic devices or CPLDs, however, the invention can be applied to other programmable devices and routing resources. In routing a set of signals through an upstream interconnect matrix or PIM, the method determines a set of high priority signals. In routing the upstream PIM, the method uses a Maximum Bipartite Matching process in one embodiment to route the original signals once. The duplicated high priority signals are then routed and sent to the input array of the downstream interconnect matrix along with the originally routed signals. From the originally routed signals and the duplicate signals, the downstream interconnect matrix routes each unique signal once and only once depending on the available routing resources. The method also uses a technique for preventing the simultaneous routing of duplicate signals through the downstream interconnect matrix and ensuring that one, and only one, copy of any signal arrives at the destination output array.

    摘要翻译： 一种用于通过可编程逻辑设备中的互连矩阵路由信号的方法和系统，使得可以减少下行路由故障。 在一个实施例中，本发明用于改进复杂可编程逻辑器件或CPLD中的布线，然而，本发明可以应用于其他可编程器件和布线资源。 在通过上游互连矩阵或PIM路由一组信号时，该方法确定一组高优先级信号。 在路由上游PIM时，该方法在一个实施例中使用最大二分组匹配过程来路由原始信号一次。 然后将重复的高优先级信号路由并发送到下游互连矩阵的输入阵列以及原始路由信号。 根据原始路由信号和重复信号，下游互连矩阵根据可用的路由资源路由每个唯一信号一次且仅一次。 该方法还使用一种技术来防止重复信号通过下游互连矩阵的同时路由，并确保任何信号的一个且仅一个副本到达目的地输出阵列。

    Methods and apparatuses for automated circuit design
    10.
    发明授权
    Methods and apparatuses for automated circuit design 有权
    自动化电路设计方法和装置

    公开(公告)号：US08291356B2

    公开(公告)日：2012-10-16

    申请号：US12580796

    申请日：2009-10-16

    申请人： Bing Tian ,  Kenneth S. McElvain

    发明人： Bing Tian ,  Kenneth S. McElvain

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5045 ,  G06F17/5077

    摘要： Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a logic function feeding a carry chain is implemented through extending the carry chain and through using the extended portion of the carry chain. In one aspect of an embodiment, control/non-control loads are separated from each other through replicating the driver elements of the mixed control/non-control loads. In one aspect of an embodiment, a read only memory (ROM) is implemented using a random access memory (RAM). In one embodiment, a register at the input side of the ROM is generated through inserting a register that is clocked at an inverted clock signal or through retiming a register from the output side of the ROM.

    摘要翻译： 自动合成电路的方法和装置。 在一个实施例的一个方面，通过延伸进位链和通过使用进位链的延伸部分来实现进给进位链的逻辑功能。 在一个实施例的一个方面，控制/非控制负载通过复制混合控制/非控制负载的驱动元件彼此分离。 在一个实施例的一个方面，使用随机存取存储器（RAM）来实现只读存储器（ROM）。 在一个实施例中，通过插入以反相时钟信号计时的寄存器或通过从ROM的输出侧重新定时寄存器来产生在ROM的输入侧的寄存器。