摘要:
An image sensor for three-dimensional (“3D”) imaging includes a first, a second, and a third pixel unit, where the second pixel unit is disposed between the first and third pixel units. Optical filters included in the pixel units are disposed on a light incident side of the image sensor to filter polarization-encoded light having a first polarization and a second polarization to photosensing regions of the pixel units. The first pixel unit includes a first optical filter having the first polarization, the second pixel unit includes a second optical filter having the second polarization, and the third pixel unit includes a third optical filter having the first polarization.
摘要:
An image sensor for three-dimensional (“3D”) imaging includes a first, a second, and a third pixel unit, where the second pixel unit is disposed between the first and third pixel units. Optical filters included in the pixel units are disposed on a light incident side of the image sensor to filter polarization-encoded light having a first polarization and a second polarization to photosensing regions of the pixel units. The first pixel unit includes a first optical filter having the first polarization, the second pixel unit includes a second optical filter having the second polarization, and the third pixel unit includes a third optical filter having the first polarization.
摘要:
An integrated circuit system includes a first device wafer having a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer having a second semiconductor layer proximate to a second metal layer including a second conductor is disposed within a second metal layer oxide. A frontside of the first device wafer is bonded to a frontside of the second device wafer at a bonding interface. A conductive path couples the first conductor to the second conductor through the bonding interface. A first metal EMI shield is disposed in one of the first metal oxide layer and second metal layer oxide layer. The first EMI shield is included in a metal layer of said one of the first metal oxide layer and the second metal layer oxide layer nearest to the bonding interface.
摘要:
An apparatus includes an image sensor with a frontside and a backside. The image sensor includes an active circuit region and bonding pads. The active circuit region has a first shape that is substantially rectangular. The substantially rectangular first shape has first chamfered corners. A perimeter of the frontside of the image sensor has a second shape that is substantially rectangular. The second substantially rectangular shape has second chamfered corners. The bonding pads are disposed on the frontside of the image sensor. The bonding pads are disposed between the first chamfered corners and the second chamfered corners. The first shape is disposed inside the second shape.
摘要:
An example image sensor system includes an image sensor having a first terminal and a host controller coupled to the first terminal. Logic is included in the image sensor system, that when executed transfers analog image data from the image sensor to the host controller through the first terminal of the image sensor and also transfers one or more digital control signals between the image sensor and the host controller through the same first terminal.
摘要:
An apparatus includes an image sensor with a frontside and a backside. The image sensor includes an active circuit region and bonding pads. The active circuit region has a first shape that is substantially rectangular. The substantially rectangular first shape has first chamfered corners. A perimeter of the frontside of the image sensor has a second shape that is substantially rectangular. The second substantially rectangular shape has second chamfered corners. The bonding pads are disposed on the frontside of the image sensor. The bonding pads are disposed between the first chamfered corners and the second chamfered corners. The first shape is disposed inside the second shape.
摘要:
An image sensor having an image acquisition mode and an ambient light sensing mode includes a pixel array having pixel cells organized into rows and columns for capturing image data and ambient light data. Readout circuitry is coupled via column bit lines to the pixels cells to read out the image data along the column bit lines. An ambient light detection (“ALD”) unit is selectively coupled to the pixel array to readout the ambient light data and to generate an ambient light signal based on ambient light incident upon the pixel array. Control circuitry is coupled to the pixel array to control time sharing of the pixels cells between the readout circuitry during image acquisition and the ALD unit during ambient light sensing.
摘要:
An apparatus of one aspect includes an array of pixels. Each of the pixels includes a photosensitive element and a transfer transistor coupled with the photosensitive element. Each of the transfer transistors has a transfer gate. The apparatus also includes a first transfer gate off voltage supply conductor and a second transfer gate off voltage supply conductor. A circuit is coupled with the first and second transfer gate off voltage supply conductors. The circuit is operable to couple the first transfer gate off voltage supply conductor to transfer gates of a first subset of the pixels of the array. The circuit is also operable to concurrently couple the second transfer gate off voltage supply conductor to transfer gates of a second subset of the pixels of the array.
摘要:
An image sensor apparatus comprises an image sensor for generating digital images having a high dynamic range. The image sensor apparatus includes an image sensor for generating a first and a second set of digital image samples at a first bit depth, with each set of digital image samples generated by a different column readout circuit path. A processor combines the first and second set of digital image samples to generate a digital image at a second bit depth, the second bit depth higher than the first bit depth.
摘要:
A hybrid ADC having a successive approximation register (SAR) ADC mode for generating a bit of a digital signal and a ramp ADC mode for generating an additional bit of the digital signal is disclosed. When in the SAR ADC mode, a control circuit is configured to disable a ramp signal generator; disable a counter; and enable a register to control an offset stage to set the magnitude of an offset voltage that is provided to an input of a comparator of the ADC. When in the ramp ADC mode, the control circuit is configured to enable the ramp signal generator to provide a ramp signal to the input of the comparator; enable the counter to begin providing the digital count in response to the output of the comparator; and disable the register so that the offset stage is not providing the offset voltage.