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1.发明授权
公开(公告)号：US5210836A
公开(公告)日：1993-05-11
申请号：US421500
申请日：1989-10-13
CPC分类号： G06T1/20 , G06F15/8007 , F02B2075/027
摘要： A synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. The processor elements are all controlled in common by a sequencer, a state machine or a control circuit (controller) to enable operation as a parallel processing device. Each processor element includes a set of input registers, two sets of register files, a set of working registers, an arithmetic logic unit including a one-bit full adder/subtractor, and a set of output registers. In video applications each processor element operates on one pixel of a horizontal scan line and is capable of real-time digital processing of video signals. In video applications a data input control circuit including a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit is provided.
摘要翻译： 具有以线性阵列组织的多个一位处理器元件的同步矢量处理器（SVP）装置。 处理器元件都由序列发生器，状态机或控制电路（控制器）共同控制，以使得能够作为并行处理装置进行操作。 每个处理器元件包括一组输入寄存器，两组寄存器文件，一组工作寄存器，包括一位全加器/减法器的算术逻辑单元和一组输出寄存器。 在视频应用中，每个处理器元件在水平扫描线的一个像素上操作，并且能够对视频信号进行实时数字处理。 在视频应用中，提供了包括主控制器电路，垂直定时发生器电路，恒定发电机电路，水平定时发生器电路和指令发生器电路的数据输入控制电路。
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2.发明授权
公开(公告)号：US5765010A
公开(公告)日：1998-06-09
申请号：US421471
申请日：1989-10-13
CPC分类号： G06F15/8092 , H04N5/775 , F02B2075/027 , H04N5/14 , H04N9/641 , H04N9/79
摘要： A timing and control circuit and method for a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. This circuit includes a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit.
摘要翻译： 一种用于具有以线性阵列组织的多个一位处理器元件的同步矢量处理器（SVP）装置的定时和控制电路和方法。 该电路包括主控制器电路，垂直定时发生器电路，恒定发电机电路，水平定时发生器电路和指令发生器电路。
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3.发明授权
公开(公告)号：US5628025A
公开(公告)日：1997-05-06
申请号：US483778
申请日：1995-06-07
CPC分类号： G06F15/8092 , H04N5/775 , F02B2075/027 , H04N5/14 , H04N9/641 , H04N9/79
摘要： A timing and control circuit and method for a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. This circuit includes a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit.
摘要翻译： 一种用于具有以线性阵列组织的多个一位处理器元件的同步矢量处理器（SVP）装置的定时和控制电路和方法。 该电路包括主控制器电路，垂直定时发生器电路，恒定发电机电路，水平定时发生器电路和指令发生器电路。
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公开(公告)号：US5327541A
公开(公告)日：1994-07-05
申请号：US887228
申请日：1992-05-18
CPC分类号： G06F15/8092 , G06F15/8015 , F02B2075/027
摘要： An apparatus and method for performing rotation of data in a register file memory. The apparatus utilizes a rotation address generator including rotation value, modulus, and offset registers, a comparator, a data selector, logic circuitry, and a subtractor. A predetermined area (P.times.Q) of the register file memory and a rotation value corresponding to the number of bits to be rotated in the rotation area is designated by an instruction program memory. An instruction decoder signals the register file, modulus register, rotation value register, and offset register of an impending rotation of data, thereby enabling loading of the modulus and rotation value registers and resetting of the offset register. A counter provides a relative address to the comparator and data selector. The comparator compares the relative address with the output of the modulus register, determining whether selected ones of the addressed register file locations fall inside or outside of the rotation area, and send an appropriate signal to the logic circuitry, an OR gate. This OR gate also receives a rotate or not-rotate signal. Consequently, either an absolute address equal to (the value of the relative address-2 * the offset value) mod (8 * the value in the modulus register) or equal to the relative address, based on predetermined conditions, is utilized to access rotationally data from the register file.
摘要翻译： 一种用于在寄存器文件存储器中执行数据旋转的装置和方法。 该装置使用包括旋转值，模数和偏移寄存器的旋转地址生成器，比较器，数据选择器，逻辑电路和减法器。 由指令程序存储器指定寄存器文件存储器的预定区域（PxQ）和与旋转区域中要旋转的位数相对应的旋转值。 指令译码器向数据的即将转动的寄存器文件，模数寄存器，旋转值寄存器和偏移寄存器发出信号，从而可以加载模数和旋转值寄存器以及复位偏移寄存器。 计数器提供比较器和数据选择器的相对地址。 比较器将相对地址与模数寄存器的输出进行比较，确定所寻址的寄存器文件位置中选定的位置是否位于旋转区域的内部或外部，并向OR逻辑电路发送适当的信号。 该或门也接收旋转或非旋转信号。 因此，利用等于（相对地址-2 *偏移值的值）mod（8 *模数寄存器中的值）或等于相对地址的绝对地址（基于预定条件）被旋转地访问 来自寄存器文件的数据。
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5.发明授权Sequential constant generator system for indicating the last data word by using the end of loop bit having opposite digital state than other data words 失效顺序常数发生器系统，用于通过使用与其他数据字相反的数字状态的循环位的结尾来指示最后的数据字
公开(公告)号：US5452425A
公开(公告)日：1995-09-19
申请号：US163606
申请日：1993-12-07
申请人： Jim Childers , Hiroshi Miyaguchi , Peter Reinecke
发明人： Jim Childers , Hiroshi Miyaguchi , Peter Reinecke
CPC分类号： G06F15/8092 , F02B2075/027
摘要： A constant generator is described which provides a sequence of digital constants in a synchronous vector processor. The constant generator includes a constant loop memory for storing data words organized into a plurality of data constant patterns and an end of loop bit, a constant loop counter for supplying sequential addresses to the constant loop memory, and a constant loop counter controller for loading the counter with one of a set of predetermined starting addresses associated with a desired constant pattern stored in the constant loop memory. Additionally, a method of supplying a sequence of digital constants in said constant generator is disclosed and includes the steps of storing a plurality of data words in a plurality of constant patterns, where each constant pattern includes an end of loop bit, supplying an address to the constant loop memory and supplying sequential addresses to the constant loop memory.
摘要翻译： 描述了在同步向量处理器中提供数字常数序列的常数发生器。 常数发生器包括用于存储组织成多个数据常数模式和循环位结束的数据字的恒定循环存储器，用于向恒定循环存储器提供顺序地址的常数循环计数器和用于加载 计数器与存储在恒定循环存储器中的期望常数模式相关联的一组预定起始地址中的一个。 另外，公开了一种在所述常数发生器中提供数字常数序列的方法，包括以多个恒定模式存储多个数据字的步骤，其中每个常数模式包括循环位结束，向 恒定循环存储器，并向恒定循环存储器提供顺序地址。
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6.发明授权Second nearest-neighbor communication network for synchronous vector processor, systems and methods 失效用于同步向量处理器的第二最近邻通信网络，系统和方法
公开(公告)号：US5163120A
公开(公告)日：1992-11-10
申请号：US421499
申请日：1989-10-13
申请人： Jim Childers , Peter Reinecke , Hiroshi Miyaguchi
发明人： Jim Childers , Peter Reinecke , Hiroshi Miyaguchi
CPC分类号： G06F15/8015 , F02B2075/027
摘要： A synchronous vector processor SVP device having a plurality of one-bit processor elements organized in a linear array. The processor elements are all controlled in common by a sequencer, a state machine or a control circuit (controller) to enable operation as a parallel processing device. Each processor element includes a set of input registers, two sets of register files, a set of working registers, an arithmetic logic unit including a one-bit full adder/subtractor, and a set of output registers. In video applications each processor element operates on one pixel of a horizontal scan line and is capable of real-time digital processing of video signals. The SVP includes interconnecting circuitry enabling the individual processor elements to retrieve data from and transmit data to their first and second nearest neighbors on either side. At the chip level external connections are provided to enable cascading of several SVP devices.
摘要翻译： 具有以线性阵列组织的多个一位处理器元件的同步矢量处理器SVP装置。 处理器元件都由序列发生器，状态机或控制电路（控制器）共同控制，以使得能够作为并行处理装置进行操作。 每个处理器元件包括一组输入寄存器，两组寄存器文件，一组工作寄存器，包括一位全加器/减法器的算术逻辑单元和一组输出寄存器。 在视频应用中，每个处理器元件在水平扫描线的一个像素上操作，并且能够对视频信号进行实时数字处理。 SVP包括互连电路，使得各个处理器元件能够从两侧检索数据并向其第一和第二最近邻居发送数据。 在芯片级别，提供外部连接以实现若干SVP设备的级联。
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7.发明授权Circuit for continuous processing of video signals in a synchronous vector processor and method of operating same 失效用于在同步向量处理器中连续处理视频信号的电路及其操作方法
公开(公告)号：US5408673A
公开(公告)日：1995-04-18
申请号：US35519
申请日：1993-03-22
申请人： Jim Childers , Hiroshi Miyaguchi
发明人： Jim Childers , Hiroshi Miyaguchi
CPC分类号： G06F15/8092 , G06F15/8015 , F02B2075/027
摘要： A data processing apparatus includes a dual port data input register, first and second sequential ring counters, first and second register files, first and second data transfer circuits, a dual port data output register and N single bit processing elements. The dual port data input register has an M bit wide input port and an N bit wide output port. The first sequential ring counter cyclically selects one column of the data input register for input. The first data transfer circuit has a plurality of input segments, which are subsets of consecutive columns of the data input register. The first data transfer circuit transfers data from a selected row of the data input register to a selected row of the first register file for all columns of each input segment in a repetitive sequence of consecutive input segments in synchronism with said first sequential ring counter. The dual port data output register, the second register file, the second sequential ring counter and the second data transfer circuit are similarly organized to output data. Each of the N single bit processing elements is connected to a predetermined column of the first and second register files and capable of data processing operations under program control including data transfer to and from selected rows of said predetermined column of said first and second register files.
摘要翻译： 数据处理装置包括双端口数据输入寄存器，第一和第二顺序环形计数器，第一和第二寄存器文件，第一和第二数据传输电路，双端口数据输出寄存器和N个单个位处理元件。 双端口数据输入寄存器具有M位宽的输入端口和N位宽的输出端口。 第一个顺序环形计数器循环选择数据输入寄存器的一列进行输入。 第一数据传送电路具有多个输入段，它们是数据输入寄存器的连续列的子集。 第一数据传送电路与所述第一顺序环形计数器同步地将数据从数据输入寄存器的所选行传送到连续输入段的重复序列中的每个输入段的所有列的选定行。 类似地，将双端口数据输出寄存器，第二寄存器文件，第二顺序环形计数器和第二数据传送电路组织成输出数据。 N个单位处理单元中的每一个连接到第一和第二寄存器堆的预定列，并且能够进行程序控制下的数据处理操作，包括从所述第一和第二寄存器堆的所述预定列的选定行的数据传送。
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公开(公告)号：US5293637A
公开(公告)日：1994-03-08
申请号：US76277
申请日：1993-06-10
申请人： Jim Childers , Hiroshi Miyaguchi
发明人： Jim Childers , Hiroshi Miyaguchi
CPC分类号： G06F15/8007 , G06T1/20 , F02B2075/027
摘要： A synchronous vector processor SVP device having a plurality of one-bit processor elements organized in a linear array. The processor elements are all controlled in common by a sequencer, a state machine or a control circuit (controller) to enable operation as a parallel processing device. Each processor element includes a set of input registers, two sets of register files, a set of working registers, an arithmetic logic unit including a one-bit full adder/subtractor, and a set of output registers. In video applications each processor element operates on one pixel of a horizontal scan line and the SVP is capable of real-time digital processing of video signals. In video applications a data input control circuit including a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit is provided. In order to distribute variables to each processor element simultaneously the data input control circuit is provided with a set of auxiliary registers and an addressing structure to modulate one of the processor elements' working registers. In this manner variables are provided to the SVP device in lieu of a designated control instruction bit.
摘要翻译： 具有以线性阵列组织的多个一位处理器元件的同步矢量处理器SVP装置。 处理器元件都由序列发生器，状态机或控制电路（控制器）共同控制，以使得能够作为并行处理装置进行操作。 每个处理器元件包括一组输入寄存器，两组寄存器文件，一组工作寄存器，包括一位全加器/减法器的算术逻辑单元和一组输出寄存器。 在视频应用中，每个处理器元件在水平扫描线的一个像素上操作，并且SVP能够对视频信号进行实时数字处理。 在视频应用中，提供了包括主控制器电路，垂直定时发生器电路，恒定发电机电路，水平定时发生器电路和指令发生器电路的数据输入控制电路。 为了同时将变量分配给每个处理器元件，数据输入控制电路设置有一组辅助寄存器和寻址结构，以调制处理器元件的工作寄存器之一。 以这种方式，将变量提供给SVP设备来代替指定的控制指令位。
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9.发明授权Programmable horizontal line filter implemented with synchronous vector processor 失效可编程水平线滤波器采用同步矢量处理器实现
公开(公告)号：US5600582A
公开(公告)日：1997-02-04
申请号：US222775
申请日：1994-04-05
申请人： Hiroshi Miyaguchi
发明人： Hiroshi Miyaguchi
CPC分类号： H03H17/0664 , G06F15/8092 , G06F17/175
摘要： A synchronous vector processor (SVP) (30) is provided to realize a horizontal decimation filter by processing in input value through a plurality of parallel processing elements (40). A plurality of input pixel values (80) representing a horizontal line of information in a video display are input to a data input register (DIR) (31) of the SVP (30). Each of the processing elements (40) is associated with a filter output and is operable to perform all calculations necessary to realize a multi-tap filter structure for the associated output. This is achieved by first increasing the frequency of the input signal by inserting zeros therein and then performing a number of multiplications and additions to generate an output value for that processing element, this realizing an interpolation FIR filter algorithm. The finite impulse response (FIR) filter algorithm is defined by predetermined filter coefficients stored in a constant generator (71d). Each of the processing elements are utilized to multiply a plurality of near-neighbor input values with FIR filter coefficients that are obtained from a constant generator (71d). The resulting sum for each of the processing elements is then input to the a data output register (DOR) (16) as the filter output. The output of the SVP (30) is then input to line memory (90) that is operable to decimate the output of select ones of the processing elements of the SVP (30). This rearranges the outputs to decrease the number of output pixels for each line relative to the number of input pixels for each line.
摘要翻译： 提供同步向量处理器（SVP）（30）以通过多个并行处理元件（40）处理输入值来实现水平抽取滤波器。 表示视频显示中的水平线信息的多个输入像素值（80）被输入到SVP（30）的数据输入寄存器（DIR）（31）。 每个处理元件（40）与滤波器输出相关联，并且可操作以执行为相关输出实现多抽头滤波器结构所必需的所有计算。 这通过首先通过在其中插入零来增加输入信号的频率，然后执行多个乘法和加法来产生该处理元件的输出值，这实现了一种插值FIR滤波算法来实现。 有限脉冲响应（FIR）滤波算法由存储在常数发生器（71d）中的预定滤波器系数定义。 每个处理元件用于将多个近邻输入值与从常数发生器（71d）获得的FIR滤波器系数相乘。 然后将每个处理元件的结果和作为滤波器输出输入到数据输出寄存器（DOR）（16）。 然后，SVP（30）的输出被输入到行存储器（90），该存储器可操作以抽取SVP（30）的选择的处理元件的输出。 这将重新排列输出，以减少每一行相对于每行输入像素数的输出像素数。
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公开(公告)号：US5210705A
公开(公告)日：1993-05-11
申请号：US887414
申请日：1992-05-20
CPC分类号： G06T1/20 , H03H17/06 , H04N7/012 , H04N7/0132 , H04N5/14 , Y10S348/914
摘要： A single-instruction multiple-data processor (10) has an input layer especially designed for high data input and output rates. The processor (10) has a number of processing elements (20), each corresponding to incoming data samples. The processing elements (20) are interleaved so that a set of samples can be input in parallel. The processor (10) is programmable, which makes it especially useful for digital filtering. Near-neighbor communications (41) among processing elements (20) realize the delays required for horizontal filtering.
摘要翻译： 单指令多数据处理器（10）具有专为高数据输入和输出速率设计的输入层。 处理器（10）具有多个处理元件（20），每个对应于输入的数据样本。 处理元件（20）被交织，使得可以并行地输入一组样本。 处理器（10）是可编程的，这使得它对于数字滤波特别有用。 处理元件（20）中的近邻通信（41）实现了水平滤波所需的延迟。
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