公开(公告)号：US20110101440A1

公开(公告)日：2011-05-05

申请号：US12612710

申请日：2009-11-05

申请人： Jin Cai ,  Brian L. Ji ,  Tak Hung Ning

发明人： Jin Cai ,  Brian L. Ji ,  Tak Hung Ning

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/1203 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/792

摘要： A CMOS device includes a silicon substrate and an electrical insulator formed over the silicon substrate. The device also includes an access pFET formed over the electrical insulator and a first gate stack and a storage pFET formed over the electrical insulator, the storage pFET including a second source region that is co-formed with the first drain region, a second channel region, and a second drain region. The device also includes a second gate stack including a second dielectric layer formed above the second channel region and a floating gate electrode formed above the second gate dielectric layer.

摘要翻译： CMOS器件包括硅衬底和形成在硅衬底上的电绝缘体。 器件还包括形成在电绝缘体上的访问pFET和形成在电绝缘体上的第一栅极堆叠和存储pFET，存储pFET包括与第一漏极区域共同形成的第二源极区域，第二沟道区域 ，和第二漏区。 该器件还包括第二栅极堆叠，其包括形成在第二沟道区上方的第二介电层和形成在第二栅极介电层上方的浮置栅电极。

公开(公告)号：US07655983B2

公开(公告)日：2010-02-02

申请号：US11757472

申请日：2007-06-04

申请人： Jin Cai ,  Tak Hung Ning

发明人： Jin Cai ,  Tak Hung Ning

IPC分类号： H01L31/119 ,  H01L21/336

CPC分类号： H01L29/78612 ,  H01L29/66772

摘要： An SOI FET device with improved floating body is proposed. Control of the body potential is accomplished by having a body doping concentration next to the source electrode higher than the body doping concentration next to the drain electrode. The high source-side dopant concentration leads to elevated forward leakage current between the source electrode and the body, which leakage current effectively locks the body potential to the source electrode potential. Furthermore, having the source-to-body junction capacitance larger than the drain-to-body junction capacitance has additional advantages in device operation. The device has no structure fabricated for the purpose of electrically connecting the body potential to other elements of the device.

摘要翻译： 提出了一种具有改进的浮体的SOI FET器件。 体电位的控制是通过使源电极旁边的体掺杂浓度高于漏电极旁边的体掺杂浓度来实现的。 高源侧掺杂剂浓度导致源电极和体之间的向前泄漏电流升高，这种泄漏电流有效地将体电位锁定到源极电位。 此外，具有大于漏极 - 体结结电容的源极 - 体结结电容在器件操作中具有额外的优点。 该装置没有制造用于将身体电势电连接到装置的其它元件的结构。

公开(公告)号：US20080296676A1

公开(公告)日：2008-12-04

申请号：US11757472

申请日：2007-06-04

申请人： Jin Cai ,  Tak Hung Ning

发明人： Jin Cai ,  Tak Hung Ning

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/78612 ,  H01L29/66772

摘要： An SOI FET device with improved floating body is proposed. Control of the body potential is accomplished by having a body doping concentration next to the source electrode higher than the body doping concentration next to the drain electrode. The high source-side dopant concentration leads to elevated forward leakage current between the source electrode and the body, which leakage current effectively locks the body potential to the source electrode potential. Furthermore, having the source-to-body junction capacitance larger than the drain-to-body junction capacitance has additional advantages in device operation. The device has no structure fabricated for the purpose of electrically connecting the body potential to other elements of the device.

摘要翻译： 提出了一种具有改进的浮体的SOI FET器件。 体电位的控制是通过使源电极旁边的体掺杂浓度高于漏电极旁边的体掺杂浓度来实现的。 高源侧掺杂剂浓度导致源电极和体之间的向前泄漏电流升高，这种泄漏电流有效地将体电位锁定到源极电位。 此外，具有大于漏极 - 体结结电容的源极 - 体结结电容在器件操作中具有额外的优点。 该装置没有制造用于将身体电势电连接到装置的其它元件的结构。

公开(公告)号：US06870213B2

公开(公告)日：2005-03-22

申请号：US10143291

申请日：2002-05-10

申请人： Jin Cai ,  Tak Hung Ning

发明人： Jin Cai ,  Tak Hung Ning

IPC分类号： H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/788 ,  H01L29/76

CPC分类号： H01L27/11521 ,  H01L21/84 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/7881

摘要： A low programming power, high speed EEPROM device is disclosed which is adapted for large scale integration. The device comprises a body, a source, a drain, and it has means for injecting a programming current into the body. The hot carriers from the body enter the floating gate with much higher efficiency than channel current carriers are capable of doing. The drain current of this device is controlled by the body bias. The device is built on an insulator, with a bottom common plate, and a top side body. These features make the device ideal for SOI and thin film technologies.

摘要翻译： 公开了一种适用于大规模集成的低编程能力的高速EEPROM器件。 该装置包括主体，源极，漏极，并且具有用于将编程电流注入到体内的装置。 来自身体的热载体进入浮动门，效率高于通道载流子能够做到的效率。 该器件的漏极电流由器件偏置控制。 该装置建立在绝缘体上，底部共同板和顶侧体。 这些特性使得器件成为SOI和薄膜技术的理想选择。

公开(公告)号：US20100105175A1

公开(公告)日：2010-04-29

申请号：US12651499

申请日：2010-01-04

申请人： Jin Cai ,  Tak Hung Ning

发明人： Jin Cai ,  Tak Hung Ning

IPC分类号： H01L21/336

CPC分类号： H01L29/78612 ,  H01L29/66772

摘要： An SOI FET device with improved floating body is proposed. Control of the body potential is accomplished by having a body doping concentration next to the source electrode higher than the body doping concentration next to the drain electrode. The high source-side dopant concentration leads to elevated forward leakage current between the source electrode and the body, which leakage current effectively locks the body potential to the source electrode potential. Furthermore, having the source-to-body junction capacitance larger than the drain-to-body junction capacitance has additional advantages in device operation. The device has no structure fabricated for the purpose of electrically connecting the body potential to other elements of the device.

摘要翻译： 提出了一种具有改进的浮体的SOI FET器件。 体电位的控制是通过使源电极旁边的体掺杂浓度高于漏电极旁边的体掺杂浓度来实现的。 高源侧掺杂剂浓度导致源电极和体之间的向前泄漏电流升高，这种泄漏电流有效地将体电位锁定到源极电位。 此外，具有大于漏极 - 体结结电容的源极 - 体结结电容在器件操作中具有额外的优点。 该装置没有制造用于将身体电势电连接到装置的其它元件的结构。

公开(公告)号：US07244976B2

公开(公告)日：2007-07-17

申请号：US11042866

申请日：2005-01-25

申请人： Jin Cai ,  Tak Hung Ning

发明人： Jin Cai ,  Tak Hung Ning

IPC分类号： H01L27/10

CPC分类号： H01L27/11521 ,  H01L21/84 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/7881

摘要： A low programming power, high speed EEPROM device is disclosed which is adapted for large scale integration. The device comprises a body, a source, a drain, and it has means for injecting a programming current into the body. The hot carriers from the body enter the floating gate with much higher efficiency than channel current carriers are capable of doing. The drain current of this device is controlled by the body bias. The device is built on an insulator, with a bottom common plate, and a top side body. These features make the device ideal for SOI and thin film technologies.

摘要翻译： 公开了一种适用于大规模集成的低编程能力的高速EEPROM器件。 该装置包括主体，源极，漏极，并且具有用于将编程电流注入到体内的装置。 来自身体的热载体进入浮动门，效率高于通道载流子能够做到的效率。 该器件的漏极电流由器件偏置控制。 该装置建立在绝缘体上，底部共同板和顶侧体。 这些特性使得器件成为SOI和薄膜技术的理想选择。

公开(公告)号：US07867866B2

公开(公告)日：2011-01-11

申请号：US12651499

申请日：2010-01-04

申请人： Jin Cai ,  Tak Hung Ning

发明人： Jin Cai ,  Tak Hung Ning

IPC分类号： H01L21/336 ,  H01L31/119

CPC分类号： H01L29/78612 ,  H01L29/66772

摘要： An SOI FET device with improved floating body is proposed. Control of the body potential is accomplished by having a body doping concentration next to the source electrode higher than the body doping concentration next to the drain electrode. The high source-side dopant concentration leads to elevated forward leakage current between the source electrode and the body, which leakage current effectively locks the body potential to the source electrode potential. Furthermore, having the source-to-body junction capacitance larger than the drain-to-body junction capacitance has additional advantages in device operation. The device has no structure fabricated for the purpose of electrically connecting the body potential to other elements of the device.

摘要翻译： 提出了一种具有改进的浮体的SOI FET器件。 体电位的控制是通过使源电极旁边的体掺杂浓度高于漏电极旁边的体掺杂浓度来实现的。 高源侧掺杂剂浓度导致源电极和体之间的向前泄漏电流升高，这种泄漏电流有效地将体电位锁定到源极电位。 此外，具有大于漏极 - 体结结电容的源极 - 体结结电容在器件操作中具有额外的优点。 该装置没有制造用于将身体电势电连接到装置的其它元件的结构。

公开(公告)号：US20110233634A1

公开(公告)日：2011-09-29

申请号：US13153806

申请日：2011-06-06

申请人： Jin Cai ,  Josephine Chang ,  Leland Chang ,  Brian L. Ji ,  Steven John Koester ,  Amlan Majumdar

发明人： Jin Cai ,  Josephine Chang ,  Leland Chang ,  Brian L. Ji ,  Steven John Koester ,  Amlan Majumdar

IPC分类号： H01L27/108

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10894

摘要： Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.

摘要翻译： 提供具有组合的存储器和逻辑功能的集成电路。 一方面，提供集成电路。 集成电路包括：衬底，其包括在BOX层上的硅层，其中硅层的选择区域具有在约3纳米和约20纳米之间的厚度; 至少一个eDRAM单元包括：至少一个传输晶体管，其具有形成在所述硅层的所述选择区域中的传输晶体管源极区域，传输晶体管漏极区域和传输晶体管沟道区域; 以及电连接到传输晶体管的电容器。

公开(公告)号：US08766410B2

公开(公告)日：2014-07-01

申请号：US13153806

申请日：2011-06-06

申请人： Jin Cai ,  Josephine Chang ,  Leland Chang ,  Brian L. Ji ,  Steven John Koester ,  Amlan Majumdar

发明人： Jin Cai ,  Josephine Chang ,  Leland Chang ,  Brian L. Ji ,  Steven John Koester ,  Amlan Majumdar

IPC分类号： H01L23/58

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10894

摘要： Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.

摘要翻译： 提供具有组合的存储器和逻辑功能的集成电路。 一方面，提供集成电路。 集成电路包括：衬底，其包括在BOX层上的硅层，其中硅层的选择区域具有在约3纳米和约20纳米之间的厚度; 至少一个eDRAM单元包括：至少一个传输晶体管，其具有形成在所述硅层的所述选择区域中的传输晶体管源极区域，传输晶体管漏极区域和传输晶体管沟道区域; 以及电连接到传输晶体管的电容器。

公开(公告)号：US07985633B2

公开(公告)日：2011-07-26

申请号：US11929943

申请日：2007-10-30

申请人： Jin Cai ,  Josephine Chang ,  Leland Chang ,  Brian L. Ji ,  Steven John Koester ,  Amlan Majumdar

发明人： Jin Cai ,  Josephine Chang ,  Leland Chang ,  Brian L. Ji ,  Steven John Koester ,  Amlan Majumdar

IPC分类号： H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10894

摘要： Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.

摘要翻译： 提供具有组合的存储器和逻辑功能的集成电路。 一方面，提供集成电路。 集成电路包括：衬底，其包括在BOX层上的硅层，其中硅层的选择区域具有在约3纳米和约20纳米之间的厚度; 至少一个eDRAM单元包括：至少一个传输晶体管，其具有形成在所述硅层的所述选择区域中的传输晶体管源极区域，传输晶体管漏极区域和传输晶体管沟道区域; 以及电连接到传输晶体管的电容器。