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15 条记录 (耗时 0.029 秒)

    Linear phase FIR sinc filter with multiplexing
    1.
    发明授权
    Linear phase FIR sinc filter with multiplexing 有权
    线性相位FIR sinc滤波器与多路复用

    公开(公告)号：US06321246B1

    公开(公告)日：2001-11-20

    申请号：US09153866

    申请日：1998-09-16

    申请人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    发明人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    IPC分类号： G06F1710

    CPC分类号： H03H17/08 ,  H03H17/0286 ,  H03H17/06 ,  H03H17/0664 ,  H03H2218/06

    摘要： A phase shifter is implemented using a polyphase filter. The filter is preferably a linear phase Finite Impulse Response (FIR) filter. The amount of delay imparted by the phase shifter is determined by a particular set of coefficients selected from a plurality of such coefficients. Storage requirements are reduced by taking advantage of symmetries in the coefficients for the filters. Memory requirements are further reduced by partitioning the polyphase filter into two polyphase filters and using one to set a rough delay amount and the other to set a fine delay amount between rough delay amount settings. The particular amount of delay may be set by an external synchronization signal.

    摘要翻译： 使用多相滤波器实现移相器。 滤波器优选为线性相位有限脉冲响应（FIR）滤波器。 由移相器给出的延迟量由从多个这样的系数中选择的一组特定系数确定。 通过利用滤波器​​的系数中的对称性来减少存储要求。 通过将多相滤波器分成两个多相滤波器并使用一个设置粗略延迟量，另一个设置粗略延迟量设置之间的精细延迟量，进一步减少存储器要求。 延迟的特定量可以由外部同步信号来设定。

    Sinc filter using twisting symmetry
    3.
    发明授权
    Sinc filter using twisting symmetry 有权
    Sinc滤波器采用扭曲对称

    公开(公告)号：US06546408B2

    公开(公告)日：2003-04-08

    申请号：US09153860

    申请日：1998-09-16

    申请人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    发明人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    IPC分类号： G06F1710

    CPC分类号： H03H17/0288 ,  H03H17/0225 ,  H03H17/0275 ,  H03H17/0282 ,  H03H17/06 ,  H03H17/0664

    摘要： A sinc filter is implemented by partitioning 1 bit wide incoming data into multibit words. The multibit words are multiplied by respective coefficient sets. Some multibit words are twisted by inverting the bit order and the multiplied using the same coefficient sets used for untwisted words. Multiplications are implemented using either look up tables or logic and the filter is implemented using only shifts and additions. The sinc filter is particularly useful applications in the field of data acquisition and particularly in the area of seismic sensing.

    摘要翻译： 通过将1位宽的输入数据分成多位字来实现sinc过滤器。 多位字乘以相应的系数组。 通过使用与未扭曲字相同的系数组来反转位顺序并使乘法相乘来扭转某些多字。 使用查找表或逻辑实现乘法，并且仅使用移位和添加实现过滤器。 sinc滤波器在数据采集领域尤其是在地震检测领域尤其有用。

    Network synchronization
    4.
    发明授权
    Network synchronization 有权
    网络同步

    公开(公告)号：US07218612B2

    公开(公告)日：2007-05-15

    申请号：US10457113

    申请日：2003-06-09

    申请人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    发明人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    IPC分类号： H04L12/26 ,  G01V1/00

    CPC分类号： H04J3/0682 ,  G01V1/22

    摘要： A network arrangement uses a poll select control protocol and a loop back arrangement at each node for equalizing transmission delay from each node to a central station. Delays at each node can be adjusted to start timing in response to a broadcast signal indicating an amount of delay to be applied from the start of a synchronization interval to the beginning of transmission of data collected at the nodes. The arrangement is particularly useful in the field of data acquisition and particularly in the area of seismic sensing.

    摘要翻译： 网络布置在每个节点处使用轮询选择控制协议和循环布置来均衡从每个节点到中心站的传输延迟。 可以调整每个节点的延迟以响应于指示从同步间隔开始到在节点处收集的数据的传输的开始而应用的延迟量的广播信号。 该方案在数据采集领域尤其在地震检测领域特别有用。

    Power on reset techniques for an integrated circuit chip
    5.
    发明授权
    Power on reset techniques for an integrated circuit chip 有权
    集成电路芯片的上电复位技术

    公开(公告)号：US06980037B1

    公开(公告)日：2005-12-27

    申请号：US09153864

    申请日：1998-09-16

    申请人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    发明人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    IPC分类号： H03L3/00 ,  H03L7/00 ,  H03L7/06

    CPC分类号： H03L7/06 ,  H03L3/00

    摘要： A power on reset circuit, preferably for an integrated circuit, detects application of voltage, starts a phase locked loop one application of voltage is detected but inhibits all clock used for digital logic operations until voltage stability is achieved. If a switched converter is used, the duty cycle of the switched converter is held at unity for a period of time before it is set to that needed to achieve the desired chip operating voltage. Clocks controlling other circuits can be released in stages after the duty cycle of the switched converter is set to its operating voltage level.

    摘要翻译： 上电复位电路，优选用于集成电路，检测电压的施加，启动锁相环，检测到电压的一个应用，但是抑制用于数字逻辑运算的所有时钟，直到达到电压稳定。 如果使用开关转换器，则在将其设置为实现期望的芯片工作电压所需的时间之前，将开关转换器的占空比保持在一定的时间。 在切换转换器的占空比被设置为其工作电压电平之后，可以分阶段释放控制其它电路的时钟。

    Noise management using a switched converter
    6.
    发明授权
    Noise management using a switched converter 有权
    使用开关转换器进行噪声管理

    公开(公告)号：US06281718B1

    公开(公告)日：2001-08-28

    申请号：US09154241

    申请日：1998-09-16

    申请人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    发明人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    IPC分类号： H03B2100

    CPC分类号： H02M3/1588 ,  Y02B70/1466

    摘要： A switched converter uses two series connected complementary CMOS devices and has a square wave source for activating one CMOS device while deactivating the other; and a break before make circuit connected between the square wave source and said complementary CMOS devices to ensure that one device is substantially completely off before the other device turns on. The switched converter is programmable as to frequency, phase and duty cycle.

    摘要翻译： 开关转换器使用两个串联的互补CMOS器件，并具有用于激活一个CMOS器件的方波源，同时使另一个CMOS器件失效; 以及在使电路连接在方波源和所述互补CMOS器件之间的断路，以确保在另一器件接通之前一个器件基本上完全截止。 开关转换器可编程为频率，相位和占空比。

    Sinc filter with selective decimation ratios
    8.
    发明授权
    Sinc filter with selective decimation ratios 有权
    具有选择性抽取比例的Sinc滤波器

    公开(公告)号：US06317765B1

    公开(公告)日：2001-11-13

    申请号：US09153862

    申请日：1998-09-16

    申请人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    发明人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    IPC分类号： G06F1717

    CPC分类号： H03H17/0282 ,  H03H17/0226 ,  H03H17/0664

    摘要： A decimation filter implements selective decimation ratios by arranging a plurality of sinc filters in different pipeline arrangements to produce the desired ratio. Power savings area achieved by implementing the sinc filters as FIR sinc filters and by implementing multiplications using look up tables. One approach uses a fixed first stage filter and one or more second stage sinc filters selected from the group comprising two 4th order, 5 tap sinc filters, a 4th order, 9 tap sinc filter; a 5th order, 6 tap sinc filter and a 6th order 7 tap sinc filter. The sinc filter is particularly useful applications in the field of data acquisition and particularly in the area of seismic sensing.

    摘要翻译： 抽取滤波器通过在不同的流水线布置中布置多个正弦滤波器来实现选择性抽取比，以产生期望的比率。 通过将sinc滤波器实现为FIR sinc滤波器并通过使用查找表来实现乘法而实现的省电区域。 一种方法使用固定的第一级滤波器和一个或多个第二级sinc滤波器，其选自包括两个4阶，5抽头sinc滤波器，第4级，9抽头sinc滤波器的组; 5号，6抽头sinc过滤器和6阶7抽头sinc过滤器。 sinc滤波器在数据采集领域尤其是在地震检测领域尤其有用。

    Correct carry bit generation
    9.
    发明授权
    Correct carry bit generation 失效
    正确的进位位产生

    公开(公告)号：US06243733B1

    公开(公告)日：2001-06-05

    申请号：US09153868

    申请日：1998-09-16

    申请人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    发明人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    IPC分类号： G06F738

    CPC分类号： G06F7/5443 ,  G06F7/49947

    摘要： A multiply add carry (MAC) circuit correctly determines the value of a carry bit when an operation X*Y+Z is undertaken, where X, Y and Z are real numbers and where an accumulator and rounding are utilized. The circuit (1) determines if the product X*Y is negative, (2) determines if the value in the accumulator is negative, (3) determines if a round bit propagates all the way to the most significant bit (MSB) position, (4) determines if the result X*Y+Accumulator+round is negative; and (5) determines a correct carry bit based on the other determinations.

    摘要翻译： 当进行X * Y + Z操作时，乘法加法（MAC）电路正确地确定进位位的值，其中X，Y和Z是实数，并且使用累加器和舍入。 电路（1）确定乘积X * Y是否为负，（2）确定累加器中的值是否为负，（3）确定一个圆比特是否一直传播到最高有效位（MSB）位置， （4）确定结果X * Y +累加器+圆是否为负; 和（5）基于其他确定来确定正确的进位位。

    Segmented chopping amplifier
    10.
    发明申请
    Segmented chopping amplifier 有权

    公开(公告)号：US20060232331A1

    公开(公告)日：2006-10-19

    申请号：US11455592

    申请日：2006-06-19

    申请人： Karl Thompson ,  John Melanson ,  Chung-Kai Chow ,  Ammisetti Prasad

    发明人： Karl Thompson ,  John Melanson ,  Chung-Kai Chow ,  Ammisetti Prasad

    IPC分类号： H03F1/02

    CPC分类号： H03F3/211 ,  H03F1/02 ,  H03F1/26 ,  H03F3/217 ,  H03F3/38 ,  H03F2200/331

    摘要： A chopping amplifier and method for chopping an input signal are disclosed. The chopping amplifier and method utilize at least two chopping amplifier stages. A chopping operation of an input signal is segmented across two or more chopping amplifier stages, and the two or more chopping amplifier stages are responsive to a master controller. Chop clock signals of the chopping amplifier stages are staggered so that they have non-overlapping periods and at least one of the chopping amplifier stages is not operating in an open loop at any given time. The non-overlapping periods are periodic so that a master chop clock of the master controller can be operated at a lower chop clock frequency. For every doubling of N number of chopping amplifier stages, magnitudes of chopping artifacts and aliased components are each respectively reduced by 3 dB.