公开(公告)号：US20060170095A1

公开(公告)日：2006-08-03

申请号：US11049407

申请日：2005-02-02

申请人： John Brennan ,  Joseph Freund ,  Ralph Moyer ,  John Osenbach ,  Hugo Safar ,  Thomas Shilling

发明人： John Brennan ,  Joseph Freund ,  Ralph Moyer ,  John Osenbach ,  Hugo Safar ,  Thomas Shilling

IPC分类号： H01L23/34

CPC分类号： H01L23/047 ,  H01L23/10 ,  H01L23/24 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/564 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0655 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/85203 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16195 ,  H01L2924/16315 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/45099

摘要： Device packages often include walls build on a heat sink that surrounds a device die that thermally interacts with the heat sink. Use of raised or depressed feature on said heat sink that contacts the walls improves the cohesiveness of the package. By appropriately positioning these features contaminant infusion into the package is improved without degrading cohesiveness.

摘要翻译： 设备包通常包括围绕与散热器热相互作用的设备管芯的散热器上的壁。 在所述散热器上使用与壁接触的凸起或凹陷特征改善了包装的内聚性。 通过适当地定位这些特征，可以改善污染物输入到包装中而不降低粘结性。

公开(公告)号：US20070241433A1

公开(公告)日：2007-10-18

申请号：US11788346

申请日：2007-04-19

申请人： Patrick Carberry ,  Jeffery Gilbert ,  George Libricz ,  Ralph Moyer ,  John Osenbach ,  Hugo Safar ,  Thomas Shilling

发明人： Patrick Carberry ,  Jeffery Gilbert ,  George Libricz ,  Ralph Moyer ,  John Osenbach ,  Hugo Safar ,  Thomas Shilling

IPC分类号： H01L23/495

CPC分类号： H01L23/49548 ,  H01L23/4334 ,  H01L23/49541 ,  H01L23/49861 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewall interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.

摘要翻译： 半导体器件封装包括包括基底和侧壁的容器。 基座被配置为支撑半导体器件芯片，并且引线框架延伸穿过至少一个侧壁。 引导框架在侧壁内的一部分具有穿透引线框架的至少一个孔。 侧壁材料延伸到孔中，从而形成强界面结合，其提供低泄漏侧壁引线框架界面。 底座具有位于至少一个侧壁的厚度内并与至少一个侧壁接合的折入特征，从而形成低泄漏的底壁 - 侧壁界面。 基座的顶表面具有凹槽，该凹槽位于至少一个侧壁的厚度内并与至少一个侧壁接合，由此增强了低泄漏的底壁 - 侧壁界面。

公开(公告)号：US20060131707A1

公开(公告)日：2006-06-22

申请号：US11015534

申请日：2004-12-18

申请人： Patrick Carberry ,  Jeffery Gilbert ,  George Libricz ,  Ralph Moyer ,  John Osenbach ,  Hugo Safar ,  Thomas Shilling

发明人： Patrick Carberry ,  Jeffery Gilbert ,  George Libricz ,  Ralph Moyer ,  John Osenbach ,  Hugo Safar ,  Thomas Shilling

IPC分类号： H01L23/495

CPC分类号： H01L23/49548 ,  H01L23/4334 ,  H01L23/49541 ,  H01L23/49861 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage-base-sidewall interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.

摘要翻译： 半导体器件封装包括包括基底和侧壁的容器。 基座被配置为支撑半导体器件芯片，并且引线框架延伸穿过至少一个侧壁。 引导框架在侧壁内的一部分具有穿透引线框架的至少一个孔。 侧壁材料延伸到孔中，从而形成强界面结合，其提供低泄漏侧壁引线框架界面。 底座具有位于至少一个侧壁的厚度内的折入特征，并与至少一个侧壁接合，从而形成低泄漏基底 - 侧壁界面。 基座的顶表面具有凹槽，该凹槽位于至少一个侧壁的厚度内并与至少一个侧壁接合，由此增强了低泄漏的底壁 - 侧壁界面。

公开(公告)号：US20060172465A1

公开(公告)日：2006-08-03

申请号：US11049246

申请日：2005-02-02

申请人： John Brennan ,  Joseph Freund ,  Jeffrey Gilbert ,  John Osenbach ,  Hugo Safar

发明人： John Brennan ,  Joseph Freund ,  Jeffrey Gilbert ,  John Osenbach ,  Hugo Safar

IPC分类号： H01L21/60

CPC分类号： H01L24/85 ,  B23K20/005 ,  H01L21/52 ,  H01L23/10 ,  H01L23/24 ,  H01L23/36 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/05599 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/484 ,  H01L2224/49109 ,  H01L2224/78313 ,  H01L2224/83801 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00

摘要： Devices such as amplifiers are built on a heat sink having a perimeter wall surrounding active electronic devices. Surprisingly formation of wire bonds to such devices tends to be degraded if they have an aspect ratio greater than 2:1. This problem is overcome by forming wire bonds before such walls have a height of 30 mils and after bond formation extending the walls to their final height.

摘要翻译： 诸如放大器的装置构建在具有围绕有源电子装置的周围壁的散热器上。 如果具有大于2:1的纵横比，则令这种装置的引线键的形成趋向于降低。 这个问题通过在这种壁的高度为30密耳之间并且在形成壁之后延伸到其最终高度之后形成线接合来克服。

公开(公告)号：US20060108672A1

公开(公告)日：2006-05-25

申请号：US10996677

申请日：2004-11-24

申请人： John Brennan ,  Joseph Freund ,  John Osenbach ,  Hugo Safar ,  Richard Shanaman

发明人： John Brennan ,  Joseph Freund ,  John Osenbach ,  Hugo Safar ,  Richard Shanaman

IPC分类号： H01L23/495 ,  H01L23/24 ,  H01L23/02

CPC分类号： H01L24/48 ,  H01L23/047 ,  H01L23/06 ,  H01L23/4827 ,  H01L23/488 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/29 ,  H01L24/31 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/2908 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4847 ,  H01L2224/83191 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/01032 ,  H01L2924/01049 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： The specification describes a technique for die bonding that is tailored to air cavity plastic packages for high power devices. The die bonding method is simple and effective, and eliminates the step of placement of solder preforms in the die bonding operation. According to the invention the die that are to be attached are pre-coated with AuSn solder. A multifunctional bonding layer is applied between the silicon die and the AuSn bonding layer. The multifunctional bonding layer comprises a multi-layer structure including Ti/Pt/Au. The chip support member comprises copper or a copper alloy. The chip support member may also be pre-coated with a bonding layer. The pre-coated die is soldered to the chip support member.

摘要翻译： 本说明书描述了针对大功率器件的空腔塑料封装而定制的芯片接合技术。 芯片接合方法简单有效，并且消除了在焊接操作中放置焊料预成型件的步骤。 根据本发明，待附接的模具预先涂覆有AuSn焊料。 在硅片和AuSn结合层之间施加多功能结合层。 多功能结合层包括包含Ti / Pt / Au的多层结构。 芯片支撑构件包括铜或铜合金。 芯片支撑构件也可以预先涂覆有结合层。 预涂模具被焊接到芯片支撑构件。

公开(公告)号：US20060139896A1

公开(公告)日：2006-06-29

申请号：US11055712

申请日：2005-02-10

申请人： Timothy Bambridge ,  Juan Herbsommer ,  Osvaldo Lopez ,  Joel Lott ,  Hugo Safar ,  Thomas Shilling

发明人： Timothy Bambridge ,  Juan Herbsommer ,  Osvaldo Lopez ,  Joel Lott ,  Hugo Safar ,  Thomas Shilling

IPC分类号： H05K7/04

CPC分类号： H05K1/021 ,  H01L23/13 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/32188 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/141 ,  H05K1/182 ,  H05K3/0061 ,  H05K3/3436 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An electronic module has a non-conducting substrate having at least one opening and a die/carrier assembly mounted within the opening in the substrate. The assembly has a conducting carrier and one or more integrated circuit (IC) dies mounted to the carrier. The invention may be implemented as an electronic system comprising a circuit board (CB) and at least one such electronic module mounted to the CB.

摘要翻译： 电子模块具有至少一个开口的非导电衬底和安装在衬底的开口内的模具/载体组件。 组件具有导电载体和安装到载体上的一个或多个集成电路（IC）管芯。 本发明可以被实现为包括电路板（CB）和安装到CB的至少一个这样的电子模块的电子系统。

公开(公告)号：US20090152983A1

公开(公告)日：2009-06-18

申请号：US12002524

申请日：2007-12-17

申请人： Rajarishi Sinha ,  Peter Ledel Gammel ,  Marco Mastrapasqua ,  Hugo Safar

发明人： Rajarishi Sinha ,  Peter Ledel Gammel ,  Marco Mastrapasqua ,  Hugo Safar

IPC分类号： H03H9/15 ,  H03H3/02

CPC分类号： H01L27/02 ,  H03H9/0557 ,  H03H9/175 ,  H03H9/564 ,  H03H9/589

摘要： The present invention is directed to monolithic integrated circuits incorporating an oscillator element that is particularly suited for use in timing applications. The oscillator element includes a resonator element having a piezoelectric material disposed between a pair of electrodes. The oscillator element also includes an acoustic confinement structure that may be disposed on either side of the resonator element. The acoustic confinement element includes alternating sets of low and high acoustic impedance materials. A temperature compensation layer may be disposed between the piezoelectric material and at least one of the electrodes. The oscillator element is monolithically integrated with an integrated circuit element through an interconnection. The oscillator element and the integrated circuit element may be fabricated sequentially or concurrently.

摘要翻译： 本发明涉及包含特别适用于定时应用的振荡器元件的单片集成电路。 振荡器元件包括具有设置在一对电极之间的压电材料的谐振元件。 振荡器元件还包括可以设置在谐振器元件的任一侧的声学限制结构。 声学限制元件包括交替的低和高声阻抗材料组。 温度补偿层可以设置在压电材料和至少一个电极之间。 振荡器元件通过互连与集成电路元件单片集成。 振荡器元件和集成电路元件可以顺序地或同时地制造。

公开(公告)号：US20050287786A1

公开(公告)日：2005-12-29

申请号：US10875029

申请日：2004-06-23

申请人： Peter Gammel ,  Bailey Jones ,  Isik Kizilyalli ,  Hugo Safar

发明人： Peter Gammel ,  Bailey Jones ,  Isik Kizilyalli ,  Hugo Safar

IPC分类号： H01L21/20 ,  H01L21/322 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/16 ,  H01L29/167 ,  H01L29/78

CPC分类号： H01L29/16 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/322 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a process for manufacturing a semiconductor device that can be incorporated into an integrated circuit. The method includes, forming a first doped layer of isotopically enriched silicon over a foundational substrate, forming a second layer of an isotopically enriched semiconductor material silicon over the first doped layer, and constructing active devices on the second layer. The device includes a first doped layer of an isotopically enriched semiconductor material and a second layer of an isotopically enriched semiconductor material located over the first doped layer, and active devices located on the second layer.

摘要翻译： 本发明提供一种可并入集成电路的半导体器件的制造方法。 该方法包括：在基底衬底上形成同位素富集的硅的第一掺杂层，在第一掺杂层上形成同位素富集的半导体材料硅的第二层，以及在第二层上构建有源器件。 该器件包括同位素富集的半导体材料的第一掺杂层和位于第一掺杂层上方的同位素富集的半导体材料的第二层以及位于第二层上的有源器件。

公开(公告)号：US08564174B2

公开(公告)日：2013-10-22

申请号：US13339505

申请日：2011-12-29

申请人： Rajarishi Sinha ,  Peter Ledel Gammel ,  Marco Mastrapasqua ,  Hugo Safar

发明人： Rajarishi Sinha ,  Peter Ledel Gammel ,  Marco Mastrapasqua ,  Hugo Safar

IPC分类号： H03H9/17

CPC分类号： H01L27/02 ,  H03H9/0557 ,  H03H9/175 ,  H03H9/564 ,  H03H9/589

摘要： The present invention is directed to monolithic integrated circuits incorporating an oscillator element that is particularly suited for use in timing applications. The oscillator element includes a resonator element having a piezoelectric material disposed between a pair of electrodes. The oscillator element also includes an acoustic confinement structure that may be disposed on either side of the resonator element. The acoustic confinement element includes alternating sets of low and high acoustic impedance materials. A temperature compensation layer may be disposed between the piezoelectric material and at least one of the electrodes. The oscillator element is monolithically integrated with an integrated circuit element through an interconnection. The oscillator element and the integrated circuit element may be fabricated sequentially or concurrently.

公开(公告)号：US08089195B2

公开(公告)日：2012-01-03

申请号：US12002524

申请日：2007-12-17

申请人： Rajarishi Sinha ,  Peter Ledel Gammel ,  Marco Mastrapasqua ,  Hugo Safar

发明人： Rajarishi Sinha ,  Peter Ledel Gammel ,  Marco Mastrapasqua ,  Hugo Safar

IPC分类号： H03H9/17

CPC分类号： H01L27/02 ,  H03H9/0557 ,  H03H9/175 ,  H03H9/564 ,  H03H9/589

摘要： The present invention is directed to monolithic integrated circuits incorporating an oscillator element that is particularly suited for use in timing applications. The oscillator element includes a resonator element having a piezoelectric material disposed between a pair of electrodes. The oscillator element also includes an acoustic confinement structure that may be disposed on either side of the resonator element. The acoustic confinement element includes alternating sets of low and high acoustic impedance materials. A temperature compensation layer may be disposed between the piezoelectric material and at least one of the electrodes. The oscillator element is monolithically integrated with an integrated circuit element through an interconnection. The oscillator element and the integrated circuit element may be fabricated sequentially or concurrently.

摘要翻译： 本发明涉及包含特别适用于定时应用的振荡器元件的单片集成电路。 振荡器元件包括具有设置在一对电极之间的压电材料的谐振元件。 振荡器元件还包括可以设置在谐振器元件的任一侧的声学限制结构。 声学限制元件包括交替的低和高声阻抗材料组。 温度补偿层可以设置在压电材料和至少一个电极之间。 振荡器元件通过互连与集成电路元件单片集成。 振荡器元件和集成电路元件可以顺序地或同时地制造。