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公开(公告)号：US09006827B2
公开(公告)日：2015-04-14
申请号：US13292629
申请日：2011-11-09
CPC分类号： H01L21/84 , H01L27/1108 , H01L27/1203
摘要： A radiation hardened static memory cell, methods of manufacture and design structures are provided. The method includes forming one or more first gate stacks and second gate stacks on a substrate. The method further includes providing a shallow implant process for the one or more first gate stacks such that diffusion regions of the one or more first gate stacks are non-butted junction regions. The method further includes providing a deep implant process for the one or more second gates stack such that diffusions regions of the one or more second gate stacks are butted junction regions.
摘要翻译： 提供了辐射硬化的静电记忆单元，制造方法和设计结构。 该方法包括在衬底上形成一个或多个第一栅极叠层和第二栅极叠层。 该方法还包括为一个或多个第一栅极堆叠提供浅注入工艺，使得一个或多个第一栅极叠层的扩散区域是非对接结的区域。 所述方法还包括为所述一个或多个第二栅极堆叠提供深度注入工艺，使得所述一个或多个第二栅极叠层的扩散区域为对接结区域。
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公开(公告)号：US06598182B1
公开(公告)日：2003-07-22
申请号：US09408352
申请日：1999-09-29
IPC分类号： H02H305
CPC分类号： G01R31/2858
摘要： A system for stressing and monitoring an electrical device, such that the imposed stress conditions may be terminated at electronic speeds, thereby preventing destruction of the device under test. The system includes stress channels each paired with a control and monitor circuit, such that the control and monitor circuit may shut down the stress if a limiting stress level is detected by the control and monitor circuit. A microprocessor is used to communicate via a digital control bus with each of the paired stress channels and control and monitor circuits to determine the status of the stress channel; control the stress input; and enable or disable the control and monitor circuits. A computer is used to communicate with the microprocessor through a serial interface.
摘要翻译： 一种用于对电气设备进行应力和监测的系统，使得施加的应力条件可以电子速度终止，从而防止被测设备的破坏。 该系统包括每个与控制和监视电路配对的应力通道，使得如果控制和监视电路检测到限制应力水平，则控制和监视电路可以关闭应力。 微处理器用于通过数字控制总线与每个配对应力通道和控制和监视电路进行通信，以确定应力通道的状态; 控制压力输入; 并启用或禁用控制和监视电路。 计算机用于通过串行接口与微处理器进行通信。
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3.发明授权公开(公告)号：US07602265B2
公开(公告)日：2009-10-13
申请号：US11163485
申请日：2005-10-20
申请人： Hariklia Deligianni , Robert D. Edwards , Thomas J. Fleischman , Robert A. Groves , Charles J. Montrose , Richard P. Volant , Ping-Chuan Wang
发明人： Hariklia Deligianni , Robert D. Edwards , Thomas J. Fleischman , Robert A. Groves , Charles J. Montrose , Richard P. Volant , Ping-Chuan Wang
IPC分类号： H01H51/22
CPC分类号： H01H59/0009
摘要： The present invention provides multiple test structures for performing reliability and qualification tests on MEMS switch devices. A Test structure for contact and gap characteristic measurements is employed having a serpentine layout simulates rows of upper and lower actuation electrodes. A cascaded switch chain test is used to monitor process defects with large sample sizes. A ring oscillator is used to measure switch speed and switch lifetime. A resistor ladder test structure is configured having each resistor in series with a switch to be tested, and having each switch-resistor pair electrically connected in parallel. Serial/parallel test structures are proposed with MEMS switches working in tandem with switches of established technology. A shift register is used to monitor the open and close state of the MEMS switches. Pull-in voltage, drop-out voltage, activation leakage current, and switch lifetime measurements are performed using the shift register.
摘要翻译： 本发明提供用于在MEMS开关装置上执行可靠性和鉴定测试的多个测试结构。 采用具有蛇形布局的接触和间隙特性测量的测试结构来模拟上下驱动电极的行。 级联交换链测试用于监控大样本量的过程缺陷。 环形振荡器用于测量开关速度和开关寿命。 电阻梯形测试结构被配置为具有与要测试的开关串联的每个电阻器，并且每个开关电阻器对并联电连接。 提出了串联/并联测试结构，其中MEMS开关与成熟技术的开关串联工作。 移位寄存器用于监测MEMS开关的开启和关闭状态。 使用移位寄存器执行拉入电压，掉电电压，启动漏电流和开关寿命测量。
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4.发明申请METHOD FOR INFORMATION TRANSFER IN A VOLTAGE-DRIVEN INTELLIGENT CHARACTERIZATION BENCH FOR SEMICONDUCTOR 审中-公开用于半导体电压驱动智能表征的信息传输方法公开(公告)号：US20120179943A1
公开(公告)日：2012-07-12
申请号：US12985459
申请日：2011-01-06
CPC分类号： G06F11/2273 , G11C29/006 , G11C29/06 , G11C29/56 , G11C2029/5602
摘要： A method for transmitting data from test device to a storage device via a parallel bus. The methods comprising the steps of setting a flag to indicate that data is available, reading the data, setting a flag to indicate the data was read. In addition test parameters are sent to the test device from the storage device, the method comprises the steps of checking to see if a test device is ready to receive data, transferring the test parameters, identifying the next channel to update.
摘要翻译： 一种通过并行总线从测试设备向存储设备发送数据的方法。 所述方法包括以下步骤：设置标志以指示数据可用，读取数据，设置用于指示数据的标志。 此外，测试参数从存储设备发送到测试设备，该方法包括检查测试设备是否准备好接收数据，传送测试参数，识别下一个信道进行更新的步骤。
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公开(公告)号：US06940285B2
公开(公告)日：2005-09-06
申请号：US10250272
申请日：2003-06-19
IPC分类号： G01R31/02 , G01R31/327 , H01H11/00 , H01H59/00
CPC分类号： H01H11/0062 , B81C99/005 , H01H59/0009
摘要： A system and method for testing performance characteristics of a MEMs device includes an activation driver configured to receive and drive a waveform to an activation side of the micro electromechanical device and configured to provide readback of an activation voltage and activation current drawn by activation of the micro electromechanical device. A switch driver configured to provide a load to a switch side of the micro electromechanical device provides readback of a load voltage and a load current drawn by the micro electromechanical device. A contact-closure counter and master control card (MCC) is included to control the activation and switch drivers while a digital volt meter (DVM) is in operable communication with the micro electromechanical device to read back analog readback. An analog multiplexer provides the analog readback to a corresponding activation driver or switch driver. A computer having software provides system control, data acquisition, data storage, and data analysis is in operable communication with the multiplexer, DVM and MCC.
摘要翻译： 用于测试MEMs器件的性能特性的系统和方法包括激活驱动器，其被配置为接收并驱动波形到微机电装置的激活侧，并且被配置为提供激活电压的读回和通过激活微机 机电装置。 配置为向微机电装置的开关侧提供负载的开关驱动器提供对由微机电装置吸取的负载电压和负载电流的回读。 包括触点闭合计数器和主控卡（MCC）以控制激活和切换驱动器，而数字电压表（DVM）可与微机电装置可操作地通信以读回模拟回读。 模拟多路复用器将模拟回读提供给相应的激活驱动器或开关驱动器。 具有软件的计算机提供系统控制，数据采集，数据存储和数据分析与多路复用器DVM和MCC可操作地通信。
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公开(公告)号：US09043179B2
公开(公告)日：2015-05-26
申请号：US12985443
申请日：2011-01-06
IPC分类号： G01R31/00 , G01R31/14 , G01R31/319 , G01R31/3193
CPC分类号： G01R31/2834 , G01R31/2607 , G01R31/2851 , G01R31/31924 , G01R31/31935
摘要： A system for testing a plurality of transistors on a wafer having a storage device or personal computer connected via a bus to a plurality of drivers. Each of the voltage drivers having a microcontroller adapted to receive test parameters and provide test data from a plurality of voltage drivers. By utilizing a bus structure, the personal computer can look on one bus for flags indicating test data is available from a driver and receive the data. In addition a bus may be used to provide test parameters to the drivers. In this manner, multiple drivers may be run at the same time incorporating multiple tests. When data is available it is transferred to the personal computer, for providing test parameters to a plurality of drivers, and connected via a second bus for receiving test results from the plurality of drivers.
摘要翻译： 一种用于测试晶片上的多个晶体管的系统，具有经由总线连接到多个驱动器的存储装置或个人计算机。 每个电压驱动器具有微控制器，其适于接收测试参数并从多个电压驱动器提供测试数据。 通过利用总线结构，个人计算机可以在一个总线上查看标志，指示测试数据可从驱动器获得并接收数据。 此外，还可以使用总线为驱动程序提供测试参数。 以这种方式，可以同时运行多个驱动程序并入多个测试。 当数据可用时，它被传送到个人计算机，用于向多个驱动器提供测试参数，并且经由第二总线连接以从多个驱动器接收测试结果。
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公开(公告)号：US06437956B1
公开(公告)日：2002-08-20
申请号：US09590993
申请日：2000-06-09
申请人： Charles J. Montrose
发明人： Charles J. Montrose
IPC分类号： H02H900
CPC分类号： G01R31/2642 , G01R31/2608 , H03K17/08146 , H03K17/785
摘要： A stress-driver circuit for providing a constant voltage (Vce) and a constant current (I=Vin/R) to a bipolar transistor under test. The circuit includes a power source, an op-amp, a FET, and the bipolar transistor. The power source is connected to the bipolar transistor collector. The op-amp has a positive input biased at input voltage (Vin) and a negative input having a feedback loop connected to the bipolar transistor emitter. The op-amp output is connected to the FET gate, the FET drain is connected to the power supply, and the FET source is biased to ground through a first resistor and connected to the base of the bipolar transistor. The second resistor is connected at one end to the bipolar transistor emitter and biased to ground at the other end. An automatic trip circuit may be provided to cut off power to the bipolar transistor if the current at the bipolar transistor collector exceeds a predetermined value. One or more parameter readback circuits may be provided in predetermined areas of the stress-driver circuit, each readback circuit providing a readout of current, voltage, or both.
摘要翻译： 用于向被测双极晶体管提供恒定电压（Vce）和恒定电流（I = Vin / R）的应力驱动电路。 电路包括电源，运算放大器，FET和双极晶体管。 电源连接到双极晶体管集电极。 运算放大器具有偏置于输入电压（Vin）的正输入和具有连接到双极晶体管发射极的反馈环路的负输入。 运算放大器输出连接到FET栅极，FET漏极连接到电源，FET源通过第一个电阻器偏置到地，并连接到双极晶体管的基极。 第二电阻器的一端连接到双极晶体管发射极，另一端被偏压到地。 如果双极晶体管集电极处的电流超过预定值，则可以提供自动跳闸电路来切断双极晶体管的电源。 可以在应力驱动器电路的预定区域中提供一个或多个参数回读电路，每个回读电路提供电流，电压或两者的读出。
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8.发明授权Voltage driver for a voltage-driven intelligent characterization bench for semiconductor 有权用于半导体电压驱动智能化测试台的电压驱动器公开(公告)号：US08615373B2
公开(公告)日：2013-12-24
申请号：US12985462
申请日：2011-01-06
申请人： Charles J. Montrose
发明人： Charles J. Montrose
CPC分类号： G01R31/2621 , G01R31/2841
摘要： A voltage driver is provided having an input to receive test parameters from a microcontroller. The voltage driver having a first amplifier to provide an input to a first switch, based on the test parameters. The first switch having an output to a first connector such as a probe adapted to be connected to a device under test or DUT. A second switch having an input from a second connector to the device under test, the output of the second switch connected to a ground. A third switch has an input connected to the second switch input, the third switch having an output connected to the first connector to the device under test, wherein the first switch is open, and the second and third switch are closed to set the first connector and the second connector to ground. A buffer is provided such that the microcontroller is sets the test parameters in the first voltage driver, the first voltage driver is adapted to provide test data to the buffer. The device is set such that all of the inputs may be set to ground to minimize the possibility of electrostatic discharge building up on the probes and damaging the DUT.
摘要翻译： 提供具有用于从微控制器接收测试参数的输入的电压驱动器。 电压驱动器具有第一放大器，以基于测试参数向第一开关提供输入。 第一开关具有到适于连接到被测器件或DUT的第一连接器的输出，例如探头。 第二开关具有从第二连接器到被测器件的输入，第二开关的输出连接到地。 第三开关具有连接到第二开关输入的输入端，第三开关具有连接到被测器件的第一连接器的输出端，其中第一开关断开，第二和第三开关闭合以将第一连接器 而第二个连接器接地。 提供缓冲器，使得微控制器将测试参数设置在第一电压驱动器中，第一电压驱动器适于向缓冲器提供测试数据。 该设备被设置为使得所有输入可以被设置为接地以最小化在探针上建立静电放电并损坏DUT的可能性。
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9.发明申请VOLTAGE DRIVER FOR A VOLTAGE-DRIVEN INTELLIGENT CHARACTERIZATION BENCH FOR SEMICONDUCTOR 有权用于半导体电压驱动智能特征的电压驱动器公开(公告)号：US20120179410A1
公开(公告)日：2012-07-12
申请号：US12985462
申请日：2011-01-06
申请人： Charles J. Montrose
发明人： Charles J. Montrose
CPC分类号： G01R31/2621 , G01R31/2841
摘要： A voltage driver is provided having an input to receive test parameters from a microcontroller. The voltage driver having a first amplifier to provide an input to a first switch, based on the test parameters. The first switch having an output to a first connector such as a probe adapted to be connected to a device under test or DUT. A second switch having an input from a second connector to the device under test, the output of the second switch connected to a ground. A third switch has an input connected to the second switch input, the third switch having an output connected to the first connector to the device under test, wherein the first switch is open, and the second and third switch are closed to set the first connector and the second connector to ground. A buffer is provided such that the microcontroller is sets the test parameters in the first voltage driver, the first voltage driver is adapted to provide test data to the buffer. The device is set such that all of the inputs may be set to ground to minimize the possibility of electrostatic discharge building up on the probes and damaging the DUT.
摘要翻译： 提供具有用于从微控制器接收测试参数的输入的电压驱动器。 电压驱动器具有第一放大器，以基于测试参数向第一开关提供输入。 第一开关具有到适于连接到被测器件或DUT的第一连接器的输出，例如探头。 第二开关具有从第二连接器到被测器件的输入，第二开关的输出连接到地。 第三开关具有连接到第二开关输入的输入端，第三开关具有连接到被测器件的第一连接器的输出端，其中第一开关断开，第二和第三开关闭合以将第一连接器 而第二个连接器接地。 提供缓冲器，使得微控制器将测试参数设置在第一电压驱动器中，第一电压驱动器适于向缓冲器提供测试数据。 该设备被设置为使得所有输入可以被设置为接地以最小化在探针上建立静电放电并损坏DUT的可能性。
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公开(公告)号：US20120179409A1
公开(公告)日：2012-07-12
申请号：US12985443
申请日：2011-01-06
IPC分类号： G06F19/00
CPC分类号： G01R31/2834 , G01R31/2607 , G01R31/2851 , G01R31/31924 , G01R31/31935
摘要： A system for testing a plurality of transistors on a wafer having a storage device or personal computer connected via a bus to a plurality of drivers. Each of the voltage drivers having a microcontroller adapted to receive test parameters and provide test data from a plurality of voltage drivers. By utilizing a bus structure, the personal computer can look on one bus for flags indicating test data is available from a driver and receive the data. In addition a bus may be used to provide test parameters to the drivers. In this manner, multiple drivers may be run at the same time incorporating multiple tests. When data is available it is transferred to the personal computer, for providing test parameters to a plurality of drivers, and connected via a second bus for receiving test results from the plurality of drivers.
摘要翻译： 一种用于测试晶片上的多个晶体管的系统，具有经由总线连接到多个驱动器的存储装置或个人计算机。 每个电压驱动器具有微控制器，其适于接收测试参数并从多个电压驱动器提供测试数据。 通过利用总线结构，个人计算机可以在一个总线上查看标志，指示测试数据可从驱动器获得并接收数据。 此外，还可以使用总线为驱动程序提供测试参数。 以这种方式，可以同时运行多个驱动程序并入多个测试。 当数据可用时，它被传送到个人计算机，用于向多个驱动器提供测试参数，并且经由第二总线连接以从多个驱动器接收测试结果。
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