公开(公告)号：US07736915B2

公开(公告)日：2010-06-15

申请号：US11276248

申请日：2006-02-21

申请人： John M. Aitken ,  Ethan Harrison Cannon ,  Alvin Wayne Strong

发明人： John M. Aitken ,  Ethan Harrison Cannon ,  Alvin Wayne Strong

IPC分类号： H01L21/00 ,  H01L31/00 ,  H01L31/0248 ,  H01L31/0352

CPC分类号： H01L21/743 ,  H01L21/76275

摘要： A method for neutralizing trapped charges in a buried oxide layer. The method includes providing a semiconductor structure which includes (a) a semiconductor layer, (b) a charge accumulation layer on top of the semiconductor layer, and (c) a doped region in direct physical contact with the semiconductor layer, wherein the charge accumulation layer comprises trapped charges of a first sign, and wherein the doped region and the semiconductor layer form a P-N junction diode. Next, free charges are generated in the P-N junction diode, wherein the free charges are of a second sign opposite to the first sign. Next, the free charges are accelerated towards the charge accumulation layer, resulting in some of the free charges entering the charge accumulation layer and neutralizing some of the trapped charges in the charge accumulation layer.

摘要翻译： 一种用于中和掩埋氧化物层中的俘获电荷的方法。 该方法包括提供半导体结构，该半导体结构包括（a）半导体层，（b）半导体层顶部的电荷累积层，和（c）与该半导体层直接物理接触的掺杂区域，其中电荷累积 层包括第一符号的俘获电荷，并且其中所述掺杂区域和所述半导体层形成PN结二极管。 接下来，在P-N结二极管中产生自由电荷，其中自由电荷是与第一符号相反的第二符号。 接下来，免费电荷朝向电荷累积层加速，导致一些自由电荷进入电荷累积层并中和电荷累积层中的一些俘获电荷。

公开(公告)号：US20100237475A1

公开(公告)日：2010-09-23

申请号：US12792837

申请日：2010-06-03

申请人： John M. Aitken ,  Ethan Harrison Cannon ,  Alvin Wayne Strong

发明人： John M. Aitken ,  Ethan Harrison Cannon ,  Alvin Wayne Strong

IPC分类号： H01L29/06

CPC分类号： H01L21/743 ,  H01L21/76275

摘要： A semiconductor structure. The semiconductor structure includes a semiconductor layer, a charge accumulation layer on top of the semiconductor layer, a doped region in direct physical contact with the semiconductor layer; and a device layer on and in direct physical contact with the charge accumulation layer. The charge accumulation layer includes trapped charges of a first sign. The doped region and the semiconductor layer forms a P-N junction diode. The P-N junction diode includes free charges of a second sign opposite to the first sign. The trapped charge in the charge accumulation layer exceeds a preset limit above which semiconductor structure is configured to malfunction. A first voltage is applied to the doped region. A second voltage is applied to the semiconductor layer. A third voltage is applied to the device layer. The third voltage exceeds the first voltage and the second voltage.

摘要翻译： 半导体结构。 半导体结构包括半导体层，在半导体层顶部的电荷累积层，与半导体层直接物理接触的掺杂区域; 以及与电荷累积层直接物理接触的器件层。 电荷累积层包括第一符号的俘获电荷。 掺杂区域和半导体层形成P-N结二极管。 P-N结二极管包括与第一个符号相反的第二个符号的免费电荷。 电荷累积层中的俘获电荷超过预设极限，超过该限制，半导体结构被配置为故障。 第一电压被施加到掺杂区域。 向半导体层施加第二电压。 第三电压被施加到器件层。 第三电压超过第一电压和第二电压。

公开(公告)号：US08035200B2

公开(公告)日：2011-10-11

申请号：US12792837

申请日：2010-06-03

申请人： John M. Aitken ,  Ethan Harrison Cannon ,  Alvin Wayne Strong

发明人： John M. Aitken ,  Ethan Harrison Cannon ,  Alvin Wayne Strong

IPC分类号： H01L29/786 ,  H01L23/62 ,  H01L23/58 ,  H01L27/12

CPC分类号： H01L21/743 ,  H01L21/76275

摘要： A semiconductor structure. The semiconductor structure includes a semiconductor layer, a charge accumulation layer on top of the semiconductor layer, a doped region in direct physical contact with the semiconductor layer; and a device layer on and in direct physical contact with the charge accumulation layer. The charge accumulation layer includes trapped charges of a first sign. The doped region and the semiconductor layer forms a P−N junction diode. The P−N junction diode includes free charges of a second sign opposite to the first sign. The trapped charge in the charge accumulation layer exceeds a preset limit above which semiconductor structure is configured to malfunction. A first voltage is applied to the doped region. A second voltage is applied to the semiconductor layer. A third voltage is applied to the device layer. The third voltage exceeds the first voltage and the second voltage.

摘要翻译： 半导体结构。 半导体结构包括半导体层，在半导体层顶部的电荷累积层，与半导体层直接物理接触的掺杂区域; 以及与电荷累积层直接物理接触的器件层。 电荷累积层包括第一符号的俘获电荷。 掺杂区域和半导体层形成P-N结二极管。 P-N结二极管包括与第一个符号相反的第二个符号的免费电荷。 电荷累积层中的俘获电荷超过预设极限，超过该限制，半导体结构被配置为故障。 第一电压被施加到掺杂区域。 向半导体层施加第二电压。 第三电压被施加到器件层。 第三电压超过第一电压和第二电压。

公开(公告)号：US06743655B2

公开(公告)日：2004-06-01

申请号：US10205527

申请日：2002-07-25

申请人： Fen Chen ,  Roger Aime Dufresne ,  Baozhen Li ,  Alvin Wayne Strong

发明人： Fen Chen ,  Roger Aime Dufresne ,  Baozhen Li ,  Alvin Wayne Strong

IPC分类号： H01L2100

CPC分类号： H01L31/028 ,  H01L31/0352 ,  Y02E10/547

摘要： A photodiode that exhibits a photo-induced negative differential resistance region upon biasing and illumination is described. The photodiode includes an N+ silicon substrate, a silicon nitride layer formed on the N+ silicon substrate, a reoxidized nitride layer formed on the silicon nitride layer and a N+ polysilicon layer formed on at least a portion of the reoxidized nitride layer.

摘要翻译： 描述了在偏压和照明时呈现光诱导的负微分电阻区域的光电二极管。 光电二极管包括N +硅衬底，形成在N +硅衬底上的氮化硅层，形成在氮化硅层上的再氧化氮化物层和形成在再氧化氮化物层的至少一部分上的N +多晶硅层。

公开(公告)号：US06445021B1

公开(公告)日：2002-09-03

申请号：US09665913

申请日：2000-09-20

申请人： Fen Chen ,  Roger Aime Dufresne ,  Baozhen Li ,  Alvin Wayne Strong

发明人： Fen Chen ,  Roger Aime Dufresne ,  Baozhen Li ,  Alvin Wayne Strong

IPC分类号： H01L27148

CPC分类号： H01L31/028 ,  H01L31/0352 ,  Y02E10/547

摘要： A photodiode that exhibits a photo-induced negative differential resistance region upon biasing and illumination is described. The photodiode includes an N+ silicon substrate, a silicon nitride layer formed on the N+ silicon substrate, a reoxidized nitride layer formed on the silicon nitride layer and a N+ polysilicon layer formed on at least a portion of the reoxidized nitride layer.

公开(公告)号：US5899724A

公开(公告)日：1999-05-04

申请号：US647392

申请日：1996-05-09

申请人： David Mark Dobuzinsky ,  Stephen Gerard Fugardi ,  Erwin Hammerl ,  Herbert Lei Ho ,  Samuel C. Ramac ,  Alvin Wayne Strong

发明人： David Mark Dobuzinsky ,  Stephen Gerard Fugardi ,  Erwin Hammerl ,  Herbert Lei Ho ,  Samuel C. Ramac ,  Alvin Wayne Strong

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/20

CPC分类号： H01L28/24

摘要： According to the preferred embodiment of the present invention, an improved resistor and method of fabrication is provided. The method for fabricating a resistive element into an integrated circuit semiconductor device comprises the steps of: depositing a dielectric film, such as silicon nitride; depositing a titanium film upon the dielectric film; and annealing the titanium and dielectric films. This causes titanium to be diffused into the dielectric film. This creates a resistive element having a relatively high resistivity. The preferred embodiment method has the advantage of being easily integrated into conventional integrated circuit fabrication techniques.

摘要翻译： 根据本发明的优选实施例，提供一种改进的电阻器和制造方法。 将电阻元件制造成集成电路半导体器件的方法包括以下步骤：沉积诸如氮化硅的介电膜; 在电介质膜上沉积钛膜; 并对钛和介电膜进行退火。 这导致钛扩散到电介质膜中。 这产生具有相对较高电阻率的电阻元件。 优选的实施方式具有易于集成到常规集成电路制造技术中的优点。

公开(公告)号：US5898706A

公开(公告)日：1999-04-27

申请号：US846989

申请日：1997-04-30

申请人： Roger Aime Dufresne ,  Charles William Griffin ,  Chorng-Lii Hwang ,  William Alan Klaasen ,  Alvin Wayne Strong

发明人： Roger Aime Dufresne ,  Charles William Griffin ,  Chorng-Lii Hwang ,  William Alan Klaasen ,  Alvin Wayne Strong

IPC分类号： G01R31/28 ,  G01R31/12

CPC分类号： G01R31/2877 ,  G01R31/2856

摘要： The present invention is directed to an apparatus and method for reliability testing of an integrated circuit. The present invention provides a test structure and method for testing gate and node dielectrics of an integrated circuit wherein a self-heating gate structure is integrated with the product structure itself. Selected conductive lines within the product structure are used as heater elements to provide temperature stressing of the integrated circuit. The localized self-heating gate structure is an integral part of the product chip. Thus, etch and deposition characteristics of the test structure are kept identical to the etch and deposition characteristics of the product itself. As low-voltage technologies make it harder to obtain significant acceleration due to voltage stressing, temperature stressing may be used instead to increase acceleration.

摘要翻译： 本发明涉及一种用于集成电路的可靠性测试的装置和方法。 本发明提供了一种用于测试集成电路的栅极和节点电介质的测试结构和方法，其中自加热栅结构与产品结构本身集成。 产品结构内的所选导线用作加热元件，以提供集成电路的温度应力。 局部自加热门结构是产品芯片的组成部分。 因此，测试结构的蚀刻和沉积特性保持与产品本身的蚀刻和沉积特性相同。 由于低压技术使得由于电压应力而难以获得显着的加速度，所以可以使用温度应力来增加加速度。