公开(公告)号：US5362669A

公开(公告)日：1994-11-08

申请号：US80544

申请日：1993-06-24

申请人： John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

发明人： John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

IPC分类号： H01L21/76 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/763

CPC分类号： H01L21/31053 ,  H01L21/76229 ,  H01L21/763 ,  Y10S148/05

摘要： A method is provided for forming a fully planarized trench isolated region in a semiconductor substrate for an integrated circuit, for example, a trench isolated field oxide region, or a trench isolated semiconductor region in which thin film semiconductor devices are formed. Planarization is accomplished by a chemical mechanical polishing process in which coplanar layers of a chemical mechanical polish resistant material are provided in a centre region of wide trenches as well as on the semiconductor substrate surface adjacent the trenches. The chemical mechanical polish resistant layer in the centre region of a wide trench forms an etch stop to prevent dishing of layers filling the trench during overall wafer planarization by chemical mechanical polishing. The method is compatible with CMOS, Bipolar and Bipolar CMOS processes for submicron VLSI and ULSI integrated circuit structures.

摘要翻译： 提供了一种用于在用于集成电路的半导体衬底中形成完全平坦化的沟槽隔离区域的方法，例如沟槽隔离场氧化物区域或其中形成薄膜半导体器件的沟槽隔离半导体区域。 通过化学机械抛光工艺实现平面化，其中化学机械耐光材料的共面层设置在宽沟槽的中心区域以及邻近沟槽的半导体衬底表面上。 在宽沟槽的中心区域中的化学机械耐光层形成蚀刻停止件，以防止在通过化学机械抛光的整个晶片平面化期间填充沟槽的层的凹陷。 该方法兼容CMOS，双极和双极CMOS工艺，用于亚微米VLSI和ULSI集成电路结构。

公开(公告)号：US5773871A

公开(公告)日：1998-06-30

申请号：US638084

申请日：1996-04-25

申请人： John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

发明人： John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

IPC分类号： H01L21/3105 ,  H01L21/763 ,  H01L29/00

CPC分类号： H01L21/763 ,  H01L21/31053

摘要： An integrated circuit structure and a method of fabrication thereof are provided. In particular, fully planarized, trench isolated semiconductor regions, e.g. comprising doped polysilicon, are provided in an integrated circuit substrate. These polysilicon regions have a smooth surface, substantially coplanar with the substrate surface, provided by chemical mechanical polishing. The near zero topography substrate provides for formation thereon of integrated circuit structures including e.g. capacitors, resistors, thin film capacitors, and interconnects, in the polysilicon trench regions at the same process level as devices formed in the semiconductor substrate. Thus a simple and flexible process for formation of improved device structures is provided, compatible with known Bipolar, CMOS and Bipolar-CMOS processes.

摘要翻译： 提供一种集成电路结构及其制造方法。 特别地，完全平坦化的沟槽隔离半导体区域，例如， 包括掺杂多晶硅，设置在集成电路基板中。 这些多晶硅区域具有通过化学机械抛光提供的平滑表面，与基板表面基本上共面。 近零地形衬底提供在其上形成集成电路结构，包括例如。 电容器，电阻器，薄膜电容器和互连，在与半导体衬底中形成的器件相同的工艺级别的多晶硅沟槽区域中。 因此，提供了用于形成改进的器件结构的简单且灵活的工艺，与已知的双极，CMOS和双极CMOS工艺兼容。

公开(公告)号：US5516710A

公开(公告)日：1996-05-14

申请号：US339184

申请日：1994-11-10

申请人： John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

发明人： John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

IPC分类号： H01L21/331 ,  H01L21/60 ,  H01L29/08 ,  H01L21/265

CPC分类号： H01L21/28114 ,  H01L21/76897 ,  H01L29/0804 ,  H01L29/42376 ,  H01L29/66272

摘要： A method is provided for forming a transistor for a bipolar, CMOS, or bipolar CMOS integrated circuit. The method is applicable to forming a double polysilicon self-aligned bipolar transistor using a single masking step for defining the emitter structure with a narrow emitter-base contact area and a large emitter contact area. The method comprises selectively providing a tapered body of dielectric to mask a region of the substrate on which an emitter is to be formed. A conductive layer is provided around the tapered body to form base contact electrodes. The tapered body is selectively removed from the substrate without damaging the underlying silicon substrate, to leave a tapered opening; localized dielectric isolation is provided in the form of sidewall spacers on the first conductive layer. The tapered opening is filled with a layer of a second conductive material to form a second electrode i.e. an emitter structure. The resulting structure is fully planarized, preferably by chemical mechanical polishing, to form coplanar contact areas to the base and emitter.

摘要翻译： 提供了一种用于形成用于双极，CMOS或双极CMOS集成电路的晶体管的方法。 该方法适用于使用单个掩模步骤形成双重多晶硅自对准双极晶体管，用于限定具有窄的发射极 - 基极接触面积和大的发射极接触面积的发射极结构。 该方法包括选择性地提供电介质的锥形体以掩盖其上将形成发射极的衬底的区域。 导电层设置在锥体周围以形成基底接触电极。 锥形体从衬底选择性地移除，而不会损坏下面的硅衬底，留下锥形开口; 在第一导电层上以侧壁间隔物的形式提供局部介电隔离。 锥形开口填充有第二导电材料层以形成第二电极，即发射极结构。 所得到的结构完全平坦化，优选通过化学机械抛光，以形成与基底和发射体的共面接触面。

公开(公告)号：US5352923A

公开(公告)日：1994-10-04

申请号：US105240

申请日：1993-08-12

申请人： John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

发明人： John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

IPC分类号： H01L21/02 ,  H01L27/02

CPC分类号： H01L28/20 ,  Y10S148/136

摘要： A method is provided for forming multi-valued linear resistors for an integrated circuit using a single mask level. A plurality of trenches are defined in a substrate. Each trench has contact regions of a specific lateral dimension and a narrower portion extending therebetween. Successive conformal layers of a first dielectric layer, a first conductive layer of high resistivity and a second conductive layer of lower resistivity are provided to fill the trench. The amount of the second conductive layer which fills the trench depends on the width of the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Advantageously when the first and second conductive layers are provided from layers of undoped and doped polysilicon respectively, the trench dimensions control the amount of dopant incorporated in each region of the trench. After annealing to diffuse dopant, the wider end contact regions are heavily doped to form contact regions, and the intermediate narrow portion of the trench is doped to a level dependent on the width of the trench, thereby forming a resistive element having a resistivity inversely dependent on the trench width. The method is compatible with CMOS, Bipolar and Bipolar CMOS processes.

摘要翻译： 提供一种用于使用单个掩模级形成用于集成电路的多值线性电阻器的方法。 多个沟槽被限定在衬底中。 每个沟槽具有特定侧向尺寸的接触区域和在它们之间延伸的较窄部分。 提供第一电介质层，高电阻率的第一导电层和较低电阻率的第二导电层的连续共形层以填充沟槽。 填充沟槽的第二导电层的量取决于沟槽的宽度。 所得到的结构被平坦化，优选通过化学机械抛光来提供完全平坦化的形貌。 有利地，当第一和第二导电层分别由未掺杂和掺杂的多晶硅层提供时，沟槽尺寸控制掺杂在沟槽的每个区域中的掺杂剂的量。 在退火到扩散掺杂剂之后，较宽的端部接触区域被重掺杂以形成接触区域，并且沟槽的中间窄部分被掺杂到取决于沟槽宽度的水平，由此形成具有电阻率相反的电阻元件 在沟槽宽度上。 该方法兼容CMOS，双极和双极CMOS工艺。

公开(公告)号：US5316978A

公开(公告)日：1994-05-31

申请号：US37048

申请日：1993-03-25

申请人： John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

发明人： John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

IPC分类号： H01L21/02 ,  H01L21/3205 ,  H01L21/283

CPC分类号： H01L28/20 ,  Y10S148/136

摘要： A method is provided for forming multi-valued linear resistors for an integrated circuit using a single mask level. A plurality of trenches are defined in a substrate. Each trench has contact regions of a specific lateral dimension and a narrower portion extending therebetween. Successive conformal layers of a first dielectric layer, a first conductive layer of high resistivity and a second conductive layer of lower resistivity are provided to fill the trench. The amount of the second conductive layer which fills the trench depends on the width of the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Advantageously when the first and second conductive layers are provided from layers of undoped and doped polysilicon respectively, the trench dimensions control the amount of dopant incorporated in each region of the trench. After annealing to diffuse dopant, the wider end contact regions are heavily doped to form contact regions, and the intermediate narrow portion of the trench is doped to a level dependent on the width of the trench, thereby forming a resistive element having a resistivity inversely dependent on the trench width. The method is compatible with CMOS, Bipolar and Bipolar CMOS processes.

摘要翻译： 提供一种用于使用单个掩模级形成用于集成电路的多值线性电阻器的方法。 多个沟槽被限定在衬底中。 每个沟槽具有特定侧向尺寸的接触区域和在它们之间延伸的较窄部分。 提供第一电介质层，高电阻率的第一导电层和较低电阻率的第二导电层的连续共形层以填充沟槽。 填充沟槽的第二导电层的量取决于沟槽的宽度。 所得到的结构被平坦化，优选通过化学机械抛光来提供完全平坦化的形貌。 有利地，当第一和第二导电层分别由未掺杂和掺杂的多晶硅层提供时，沟槽尺寸控制掺杂在沟槽的每个区域中的掺杂剂的量。 在退火到扩散掺杂剂之后，较宽的端部接触区域被重掺杂以形成接触区域，并且沟槽的中间窄部分被掺杂到取决于沟槽宽度的水平，由此形成具有电阻率相反的电阻元件 在沟槽宽度上。 该方法兼容CMOS，双极和双极CMOS工艺。

公开(公告)号：US5726084A

公开(公告)日：1998-03-10

申请号：US637963

申请日：1996-04-25

申请人： John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

发明人： John M. Boyd ,  Joseph P. Ellul ,  Sing P. Tay

IPC分类号： H01L21/3105 ,  H01L21/763 ,  H01L21/8242

CPC分类号： H01L21/763 ,  H01L21/31053

摘要： A integrated circuit structure and a method of fabrication thereof are provided. In particular, fully planarized, trench isolated semiconductor regions, e.g. comprising doped polysilicon, are provided in an integrated circuit substrate. These polysilicon regions have a smooth surface, substantially coplanar with the substrate surface, provided by chemical mechanical polishing. The near zero topography substrate provides for formation thereon of integrated circuit structures including e.g. capacitors, resistors, thin film capacitors, and interconnects, in the polysilicon trench regions at the same process level as devices formed in the semiconductor substrate. Thus a simple and flexible process for formation of improved device structures is provided, compatible with known Bipolar, CMOS and Bipolar-CMOS processes.

摘要翻译： 提供集成电路结构及其制造方法。 特别地，完全平坦化的沟槽隔离半导体区域，例如， 包括掺杂多晶硅，设置在集成电路基板中。 这些多晶硅区域具有通过化学机械抛光提供的平滑表面，与基板表面基本上共面。 近零地形衬底提供在其上形成集成电路结构，包括例如。 电容器，电阻器，薄膜电容器和互连，在与半导体衬底中形成的器件相同的工艺级别的多晶硅沟槽区域中。 因此，提供了用于形成改进的器件结构的简单且灵活的工艺，与已知的双极，CMOS和双极CMOS工艺兼容。

公开(公告)号：US5614750A

公开(公告)日：1997-03-25

申请号：US496650

申请日：1995-06-29

申请人： Joseph P. Ellul ,  John M. Boyd

发明人： Joseph P. Ellul ,  John M. Boyd

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L29/417 ,  H01L29/76 ,  H01L27/082 ,  H01L27/102 ,  H01L29/94

CPC分类号： H01L21/743 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/41708

摘要： A buried layer contact for a integrated circuit structure is provided, with particular application for a contact for a buried collector of a bipolar transistor. The buried layer contact takes the form of a sinker comprising a fully recessed trench isolated structure having dielectric lined sidewalls and filled with conductive material, e.g. doped polysilicon which contacts the buried layer. The trench isolated contact is more compact than a conventional diffused sinker structure, and thus beneficially allows for reduced transistor area. Advantageously, a reduced area sinker reduces the parasitic capacitance and power dissipation. In a practical implementation, the structure provides for an annular collector contact structure to reduce collector resistance.

摘要翻译： 提供了一种用于集成电路结构的掩埋层接触，特别适用于双极晶体管的埋地集电极的接触。 掩埋层接触采取沉降片的形式，其包括完全凹陷的沟槽隔离结构，其具有电介质衬里侧壁并填充有导电材料，例如， 接触埋层的掺杂多晶硅。 沟槽隔离触点比常规扩散沉降片结构更紧凑，因此有利地减少了晶体管面积。 有利的是，减小的面积沉降片减小了寄生电容和功耗。 在实际实施中，该结构提供环形集电极接触结构以减小集电极电阻。

公开(公告)号：US5394000A

公开(公告)日：1995-02-28

申请号：US137453

申请日：1993-10-07

申请人： Joseph P. Ellul ,  John M. Boyd ,  Michael B. Rowlandson

发明人： Joseph P. Ellul ,  John M. Boyd ,  Michael B. Rowlandson

IPC分类号： H01L21/334 ,  H01L27/108 ,  H01L23/48

CPC分类号： H01L29/66181 ,  H01L27/10829

摘要： A method is provided for forming electrodes of a trench capacitor for an integrated circuit in which the number of mask levels is reduced. The method is compatible with CMOS and Bipolar CMOS processes. After defining a trench in a substrate by a conventional photoengraving step and anisotropic etching, successive conformal layers of a first dielectric layer, a first conductive layer, and subsequent conformal dielectric layers and conformal conductive layers are deposited to fill the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Each of the conductive layers form an electrode. Coplanar areas of each of the conductive layers are exposed within the trench for formation of contacts to the electrodes. Advantageously, the trench has a wide portion and a narrow portion of smaller lateral dimension. The narrow portion of the trench is filled by the first conductive layer and after planarization provides an area of sufficiently large dimension for forming a contact to the first electrode. Contact to the second electrode is made in the first portion of the trench. Thus multiple electrodes for a trench capacitor are defined by a maskless process.

摘要翻译： 提供一种形成用于集成电路的沟槽电容器的电极的方法，其中屏蔽电平的数量减少。 该方法与CMOS和双极CMOS工艺兼容。 在通过常规光刻步骤和各向异性蚀刻在衬底中限定沟槽之后，沉积第一介电层，第一导电层和随后的保形电介质层和共形导电层的连续共形层以填充沟槽。 所得到的结构被平坦化，优选通过化学机械抛光来提供完全平坦化的形貌。 每个导电层形成电极。 每个导电层的共面区域在沟槽内露出以形成与电极的接触。 有利地，沟槽具有较小部分和较小横向尺寸的窄部分。 沟槽的狭窄部分由第一导电层填充，并且在平坦化之后提供足够大的尺寸的区域以形成与第一电极的接触。 在沟槽的第一部分中形成与第二电极的接触。 因此，通过无掩模工艺来定义用于沟槽电容器的多个电极。

公开(公告)号：US5275974A

公开(公告)日：1994-01-04

申请号：US921667

申请日：1992-07-30

申请人： Joseph P. Ellul ,  John M. Boyd ,  Michael B. Rowlandson

发明人： Joseph P. Ellul ,  John M. Boyd ,  Michael B. Rowlandson

IPC分类号： H01L21/334 ,  H01L27/108 ,  H01L21/62

CPC分类号： H01L29/66181 ,  H01L27/10829

摘要： A method is provided for forming electrodes of a trench capacitor for an integrated circuit in which the number of mask levels is reduced. The method is compatible with CMOS and Bipolar CMOS processes. After defining a trench in a substrate by a conventional photoengraving step and anisotropic etching, successive conformal layers of a first dielectric layer, a first conductive layer, and subsequent conformal dielectric layers and conformal conductive layers are deposited to fill the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Each of the conductive layers form an electrode. Coplanar areas of each of the conductive layers are exposed within the trench for formation of contacts to the electrodes. Advantageously, the trench has a wide portion and a narrow portion of smaller lateral dimension. The narrow portion of the trench is filled by the first conductive layer and after planarization provides an area of sufficiently large dimension for forming a contact to the first electrode. Contact to the second electrode is made in the first portion of the trench. Thus multiple electrodes for a trench capacitor are defined by a maskless process.

摘要翻译： 提供一种形成用于集成电路的沟槽电容器的电极的方法，其中屏蔽电平的数量减少。 该方法与CMOS和双极CMOS工艺兼容。 在通过常规光刻步骤和各向异性蚀刻在衬底中限定沟槽之后，沉积第一介电层，第一导电层和随后的保形电介质层和共形导电层的连续共形层以填充沟槽。 所得到的结构被平坦化，优选通过化学机械抛光来提供完全平坦化的形貌。 每个导电层形成电极。 每个导电层的共面区域在沟槽内露出以形成与电极的接触。 有利地，沟槽具有较小部分和较小横向尺寸的窄部分。 沟槽的狭窄部分由第一导电层填充，并且在平坦化之后提供足够大的尺寸的区域以形成与第一电极的接触。 在沟槽的第一部分中形成与第二电极的接触。 因此，通过无掩模工艺来定义用于沟槽电容器的多个电极。

公开(公告)号：US09359673B2

公开(公告)日：2016-06-07

申请号：US13489235

申请日：2012-06-05

申请人： Hyungsuk Alexander Yoon ,  Mikhail Korolik ,  Fritz C. Redeker ,  John M. Boyd ,  Yezdi Dordi

发明人： Hyungsuk Alexander Yoon ,  Mikhail Korolik ,  Fritz C. Redeker ,  John M. Boyd ,  Yezdi Dordi

IPC分类号： C23C16/455 ,  C23C16/54 ,  H01L21/67 ,  H01L21/285 ,  H01L21/768

CPC分类号： C23C16/45551 ,  C23C16/45517 ,  C23C16/54 ,  H01L21/28562 ,  H01L21/76843

摘要： A proximity heads for dispensing reactants and purging gas to deposit a thin film by Atomic Layer Deposition (ALD) includes a plurality of sides. Extending over a portion of the substrate region and being spaced apart from the portion of the substrate region when present, the proximity head is rotatable so as to place each side in a direction of the substrate region, and is disposed in a vacuum chamber coupled to a carrier gas source to sustain a pressure for the proximity head during operation. Each side of the proximity head includes a gas conduit through which the reactant gas and the purging gas are sequentially dispensed, and at least two separate vacuum conduits on each side of the gas conduit to pull excess reactant gas, purging gas, or deposition byproducts from a reaction volume between a surface of the proximity head facing the substrate and the substrate.

摘要翻译： 用于分配反应物和吹扫气体以通过原子层沉积（ALD）沉积薄膜的邻近头包括多个侧面。 当衬底区域的一部分延伸并与衬底区域的部分间隔开时，邻近头部是可旋转的，以便将每个侧面放置在衬底区域的方向上，并且设置在耦合到 载体气体源，用于在操作期间维持邻近头部的压力。 邻近头部的每一侧包括气体导管，反应气体和净化气体依次分配通过该气体导管，以及在气体导管的每一侧上的至少两个独立的真空管道，以将过量的反应气体，净化气体或沉积副产物从 面对衬底的接近头的表面与衬底之间的反应体积。