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    Method of integrated circuit design by selection of noise tolerant gates
    1.
    发明授权
    Method of integrated circuit design by selection of noise tolerant gates 失效

    公开(公告)号：US06490708B2

    公开(公告)日：2002-12-03

    申请号：US09812211

    申请日：2001-03-19

    申请人： John M. Cohn ,  Scott W. Gould ,  Peter A. Habitz ,  Jose L. P. Neves ,  William F. Smith ,  Larry Wissel ,  Paul S. Zuchowski

    发明人： John M. Cohn ,  Scott W. Gould ,  Peter A. Habitz ,  Jose L. P. Neves ,  William F. Smith ,  Larry Wissel ,  Paul S. Zuchowski

    IPC分类号： G06E1750

    CPC分类号： G06F17/505

    摘要： A method of integrated circuit design using the selective replacement of increasingly noise tolerant cells is disclosed. The method involves compiling a library comprising a plurality of design element cells, sorting the library into groups of functionally-equivalent cells, and ordering the cells in each group from one extreme to the other extreme value of a featured parameter for which the integrated circuit is to be tested. Each one of the cells in the library have a known value of another parameter so that the substitution of a library cell for an original cell or another library cell does not affect the overall integrated circuit value for that known parameter. A substitution can thus be made with the knowledge that additional problems involving the known parameter are not being created. If a test of the integrated circuit discovers a problem in a particular cell's performance with regard to the featured parameter the appropriate library group is accessed and the failing cell is replaced with the first unused cell in the group. The process is repeated until the integrated circuit passes a performance test.

    Method and apparatus for manufacturing diamond shaped chips
    2.
    发明授权
    Method and apparatus for manufacturing diamond shaped chips 有权
    用于制造菱形芯片的方法和装置

    公开(公告)号：US07961932B2

    公开(公告)日：2011-06-14

    申请号：US11865728

    申请日：2007-10-01

    申请人： Robert J. Allen ,  John M. Cohn ,  Scott W. Gould ,  Peter A. Habitz ,  Juergen Koehl ,  Gustavo E. Tellez ,  Ivan L. Wemple ,  Paul S. Zuchowski

    发明人： Robert J. Allen ,  John M. Cohn ,  Scott W. Gould ,  Peter A. Habitz ,  Juergen Koehl ,  Gustavo E. Tellez ,  Ivan L. Wemple ,  Paul S. Zuchowski

    IPC分类号： G06K9/00

    CPC分类号： H01L27/0207

    摘要： In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.

    摘要翻译： 在第一方面中，用于对晶片上的芯片进行成像的本发明的装置包括具有多个倾斜侧面的组合金刚石芯片图像和切口图像。 组合的金刚石芯片图像和切口图像包括金刚石芯片图像，其包括与金刚石芯片图像的至少一个对角线平行的多个芯片图像行，并且包括与金刚石芯片图像相邻的切痕图像。 切口图像包括平行于金刚石切片图像的至少一个对角线的至少一个切痕图像行。 该装置还包括从组合的金刚石片图像和切痕图像延伸到步进器的曝光场的至少周边的阻挡材料。 在第二方面，成像装置包括n侧多边形组合芯片图像和切口图像。 还提供了制造芯片的创造性方法和根据本发明方法制造的晶片。

    Method and apparatus for manufacturing diamond shaped chips
    3.
    发明授权
    Method and apparatus for manufacturing diamond shaped chips 有权
    用于制造菱形芯片的方法和装置

    公开(公告)号：US07289659B2

    公开(公告)日：2007-10-30

    申请号：US10250295

    申请日：2003-06-20

    申请人： Robert J. Allen ,  John M. Cohn ,  Scott W. Gould ,  Peter A. Habitz ,  Juergen Koehl ,  Gustavo E. Tellez ,  Ivan L. Wemple ,  Paul S. Zuchowski

    发明人： Robert J. Allen ,  John M. Cohn ,  Scott W. Gould ,  Peter A. Habitz ,  Juergen Koehl ,  Gustavo E. Tellez ,  Ivan L. Wemple ,  Paul S. Zuchowski

    IPC分类号： G06K9/00

    CPC分类号： H01L27/0207

    摘要： In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.

    摘要翻译： 在第一方面中，用于对晶片上的芯片进行成像的本发明的装置包括具有多个倾斜侧面的组合金刚石芯片图像和切口图像。 组合的金刚石芯片图像和切口图像包括金刚石芯片图像，其包括与金刚石芯片图像的至少一个对角线平行的多个芯片图像行，并且包括与金刚石芯片图像相邻的切痕图像。 切口图像包括平行于金刚石切片图像的至少一个对角线的至少一个切痕图像行。 该装置还包括从组合的金刚石片图像和切痕图像延伸到步进器的曝光场的至少周边的阻挡材料。 在第二方面，成像装置包括n侧多边形组合芯片图像和切口图像。 还提供了制造芯片的创造性方法和根据本发明方法制造的晶片。

    Multiple supply gate array backfill structure
    6.
    发明授权
    Multiple supply gate array backfill structure 失效
    多电源门阵列回填结构

    公开(公告)号：US07095063B2

    公开(公告)日：2006-08-22

    申请号：US10249779

    申请日：2003-05-07

    申请人： John M. Cohn ,  Kevin M. Grosselfinger ,  William F. Smith ,  Paul S. Zuchowski

    发明人： John M. Cohn ,  Kevin M. Grosselfinger ,  William F. Smith ,  Paul S. Zuchowski

    IPC分类号： H01L27/10

    CPC分类号： H01L27/11803

    摘要： A multiple supply gate array structure facilitated by the provision of a shared n-well and an isolated n-well is described. The gate array structure allows implementation of a single voltage circuit or a multiple voltage circuit. In addition, the gate array structure allows metal reprogram to provide standard logic functions, or special logic functions such as a buffer function for a signal crossing a voltage island boundary. Other special logic functions may include, for example, a level-shifter function or a fence-hold function.

    摘要翻译： 描述了通过提供共享n阱和隔离的n阱来促进的多电源栅极阵列结构。 门阵列结构允许实现单电压电路或多电压电路。 此外，门阵列结构允许金属重新编程提供标准逻辑功能，或特殊逻辑功能，例如跨越电压岛边界的信号的缓冲功能。 其他特殊逻辑功能可以包括例如电平转换器功能或栅栏保持功能。

    Method for adding decoupling capacitance during integrated circuit design
    7.
    发明授权
    Method for adding decoupling capacitance during integrated circuit design 有权
    在集成电路设计期间添加去耦电容的方法

    公开(公告)号：US06523159B2

    公开(公告)日：2003-02-18

    申请号：US09761464

    申请日：2001-01-16

    申请人： Kerry Bernstein ,  John M. Cohn ,  Jose L. P. Neves

    发明人： Kerry Bernstein ,  John M. Cohn ,  Jose L. P. Neves

    IPC分类号： G06F1750

    CPC分类号： G06F17/5036

    摘要： A method and a related program storage product for adding decoupling capacitance in an integrated circuit during the floor planning stage of the integrated circuit design. The invention overlay a power grid on the floor plan and then divides the power grid into regions or macros. For each region or macro, a support decoupling capacitance value required to support a voltage of the power grid and a native capacitance value are determined. Based on those values, a required decoupling capacitance value along with its decoupling capacitance area is determined. The design is then alternated based on the decoupling capacitance area.

    摘要翻译： 一种用于在集成电路设计的平面布置阶段期间在集成电路中添加去耦电容的方法和相关程序存储产品。 本发明在平面图上覆盖电网，然后将电网划分为区域或宏。 对于每个区域或宏，确定支持电网电压所需的支持去耦电容值和固有电容值。 基于这些值，确定所需的去耦电容值及其去耦电容面积。 然后基于去耦电容面积交替设计。

    System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA
    8.
    发明授权
    System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA 失效
    使用嵌入式FPGA的冗余逻辑单元在集成电路中提供错误检测和校正能力的系统和方法

    公开(公告)号：US07644327B2

    公开(公告)日：2010-01-05

    申请号：US12049166

    申请日：2008-03-14

    申请人： John M. Cohn ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

    发明人： John M. Cohn ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318519 ,  G01R31/318558 ,  G06F11/261 ,  H03K19/00392

    摘要： A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function. All outputs in an output cone of logic of the defective logic function are identified, and the output of the FPGA is directed to the output cone of logic of the defective logic unction, such that logic EC is provided within the embedded FPGA structure of the IC chip.

    摘要翻译： 一种使用冗余逻辑单元和嵌入式现场可编程门阵列（FPGA）在IC中提供错误检测和校正能力的系统和方法。 该系统和方法提供纠错（EC），以使得能够替换在IC芯片设计中实现的故障逻辑功能，其中在IC芯片中提供至少一个嵌入式FPGA以执行逻辑功能。 如果在IC设计中识别到故障逻辑功能，嵌入式FPGA将被编程为正确执行故障逻辑功能。 识别故障逻辑功能逻辑输入锥中的所有输入，并将其引导到嵌入式FPGA中，使嵌入式FPGA执行故障逻辑功能的逻辑功能。 识别有缺陷逻辑功能的逻辑输出锥中的所有输出，并将FPGA的输出引导到故障逻辑逻辑的逻辑输出锥，使得在IC的嵌入式FPGA结构内提供逻辑EC 芯片。

    SYSTEM AND METHOD OF PROVIDING ERROR DETECTION AND CORRECTION CAPABILITY IN AN INTEGRATED CIRCUIT USING REDUNDANT LOGIC CELLS OF AN EMBEDDED FPGA
    9.
    发明申请
    SYSTEM AND METHOD OF PROVIDING ERROR DETECTION AND CORRECTION CAPABILITY IN AN INTEGRATED CIRCUIT USING REDUNDANT LOGIC CELLS OF AN EMBEDDED FPGA 失效
    使用嵌入式FPGA的冗余逻辑单元在集成电路中提供错误检测和校正能力的系统和方法

    公开(公告)号：US20080163016A1

    公开(公告)日：2008-07-03

    申请号：US12049166

    申请日：2008-03-14

    申请人： John M. Cohn ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

    发明人： John M. Cohn ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

    IPC分类号： G01R31/3177 ,  G06F11/25

    CPC分类号： G01R31/318519 ,  G01R31/318558 ,  G06F11/261 ,  H03K19/00392

    摘要： A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function. All outputs in an output cone of logic of the defective logic function are identified, and the output of the FPGA is directed to the output cone of logic of the defective logic unction, such that logic EC is provided within the embedded FPGA structure of the IC chip.

    摘要翻译： 一种使用冗余逻辑单元和嵌入式现场可编程门阵列（FPGA）在IC中提供错误检测和校正能力的系统和方法。 该系统和方法提供纠错（EC），以使得能够替换在IC芯片设计中实现的故障逻辑功能，其中在IC芯片中提供至少一个嵌入式FPGA以执行逻辑功能。 如果在IC设计中识别到故障逻辑功能，嵌入式FPGA将被编程为正确执行故障逻辑功能。 识别故障逻辑功能逻辑输入锥中的所有输入，并将其引导到嵌入式FPGA中，使嵌入式FPGA执行故障逻辑功能的逻辑功能。 识别有缺陷逻辑功能的逻辑输出锥中的所有输出，并将FPGA的输出引导到故障逻辑逻辑的逻辑输出锥，使得在IC的嵌入式FPGA结构内提供逻辑EC 芯片。

    System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA
    10.
    发明授权
    System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA 有权
    使用嵌入式FPGA的冗余逻辑单元在集成电路中提供错误检测和校正能力的系统和方法

    公开(公告)号：US07373567B2

    公开(公告)日：2008-05-13

    申请号：US10709754

    申请日：2004-05-26

    申请人： John M. Cohn ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

    发明人： John M. Cohn ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318519 ,  G01R31/318558 ,  G06F11/261 ,  H03K19/00392

    摘要： A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function. All outputs in an output cone of logic of the defective logic function are identified, and the output of the FPGA is directed to the output cone of logic of the defective logic function, such that logic EC is provided within the embedded FPGA structure of the IC chip.

    摘要翻译： 一种使用冗余逻辑单元和嵌入式现场可编程门阵列（FPGA）在IC中提供错误检测和校正能力的系统和方法。 该系统和方法提供纠错（EC），以使得能够替换在IC芯片设计中实现的故障逻辑功能，其中在IC芯片中提供至少一个嵌入式FPGA以执行逻辑功能。 如果在IC设计中识别到故障逻辑功能，嵌入式FPGA将被编程为正确执行故障逻辑功能。 识别故障逻辑功能逻辑输入锥中的所有输入，并将其引导到嵌入式FPGA中，使嵌入式FPGA执行故障逻辑功能的逻辑功能。 识别故障逻辑功能的逻辑输出锥中的所有输出，并将FPGA的输出引导到故障逻辑功能的逻辑输出锥，使得在IC的嵌入式FPGA结构内提供逻辑EC 芯片。