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52 条记录 (耗时 0.031 秒)

    Aluminum oxide LPCVD system
    3.
    发明授权
    Aluminum oxide LPCVD system 失效
    氧化铝LPCVD系统

    公开(公告)号：US5540777A

    公开(公告)日：1996-07-30

    申请号：US541284

    申请日：1995-10-12

    申请人： Steven G. Barbee ,  Jonathan D. Chapple-Sokol ,  Richard A. Conti ,  Richard Hsiao ,  James A. O'Neill ,  Narayana V. Sarma ,  Donald L. Wilson ,  Justin W.-C. Wong ,  Steven P. Zuhoski

    发明人： Steven G. Barbee ,  Jonathan D. Chapple-Sokol ,  Richard A. Conti ,  Richard Hsiao ,  James A. O'Neill ,  Narayana V. Sarma ,  Donald L. Wilson ,  Justin W.-C. Wong ,  Steven P. Zuhoski

    IPC分类号： C23C16/40 ,  C23C16/448 ,  C23C16/52 ,  H01L21/205 ,  H01L21/31 ,  H01L21/316 ,  C23C16/00

    CPC分类号： C23C16/403 ,  C23C16/4481 ,  C23C16/52

    摘要： A process and apparatus for Al.sub.2 O.sub.3 CVD on silicon wafers using aluminum tri-isopropoxide in a high-volume production environment is presented. The conditions required to use ATI in a production environment and provide maximum utilization of ATI are first of all delivery of ATI via direct evaporation. The ATI source bottle is pumped out (bypassing substrates) until propene and isopropanol signals are reduced to 1% of process pressure before start of aluminum oxide deposition. Either IR spectroscopy or mass spectrometry can be used to provide a control signal to the microprocessor controller. Heating the supplied tetramer to 120.degree. C. for two hours assures complete conversion to trimer. The ATI is stored at 90.degree. C. to minimize decomposition during idle periods and allow recovery of trimer upon return to 120.degree. C. for two hours. During periods of demand, the ATI is held at 120.degree. C. to minimize decomposition.

    摘要翻译： 介绍了在大批量生产环境中使用三异丙氧基铝的硅晶片上Al2O3 CVD的工艺和装置。 在生产环境中使用ATI并提供ATI的最大利用率所需的条件首先通过直接蒸发传送ATI。 在开始氧化铝沉积之前，将ATI源瓶泵出（旁路基板），直到丙烯和异丙醇信号降低到过程压力的1％。 可以使用红外光谱或质谱法向微处理器控制器提供控制信号。 将供应的四聚体加热至120℃保持两小时，确保完全转化为三聚体。 将ATI储存在90℃以使空闲期间的分解最小化，并允许在回到120℃回收三聚体两小时。 在需求期间，ATI保持在120℃以最小化分解。

    Integrated circuits having reduced stress in metallization
    8.
    发明授权
    Integrated circuits having reduced stress in metallization 失效
    集成电路在金属化中具有降低的应力

    公开(公告)号：US06208008B1

    公开(公告)日：2001-03-27

    申请号：US09260702

    申请日：1999-03-02

    申请人： Kenneth C. Arndt ,  Richard A. Conti ,  David M. Dobuzinsky ,  Laertis Economikos ,  Jeffrey P. Gambino ,  Peter D. Hoh ,  Chandrasekhar Narayan

    发明人： Kenneth C. Arndt ,  Richard A. Conti ,  David M. Dobuzinsky ,  Laertis Economikos ,  Jeffrey P. Gambino ,  Peter D. Hoh ,  Chandrasekhar Narayan

    IPC分类号： H01L2941

    CPC分类号： H01L21/76804 ,  H01L21/32136 ,  H01L21/76835 ,  H01L21/76885

    摘要： The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.

    摘要翻译： 通过使与金属图案化方法（例如反应离子蚀刻（RIE）和镶嵌技术）一起制造的集成电路的电介质中通常引起的应力可以通过将与形成为集成电路的一部分的特征相关联的下角 在施加外部（即钝化）层之前，例如，互连）。 关于通过金属RIE工艺形成的金属线的形成，可以使用包括产生垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤的两步金属蚀刻工艺来实现这种角圆化 或者沿着垂直侧壁的下部产生锥形间隔物。 这导致圆角的底角，其改善了上覆电介质的台阶覆盖，从而消除了裂纹的可能性。 对于由大马士革图案化的金属线，可以使用包括产生垂直侧壁的第一步骤的两步沟槽蚀刻工艺，以及沿着垂直侧壁的下部产生锥形侧壁的第二步骤来实现这种角落圆化。

    Method of eliminating a critical mask using a blockout mask and a resulting semiconductor structure
    9.
    发明授权
    Method of eliminating a critical mask using a blockout mask and a resulting semiconductor structure 失效
    使用阻挡掩模和所得半导体结构消除临界掩模的方法

    公开(公告)号：US06232222B1

    公开(公告)日：2001-05-15

    申请号：US09395418

    申请日：1999-09-14

    申请人： Michael Armacost ,  Richard A. Conti ,  Jeffrey P. Gambino ,  Jeremy K. Stephens

    发明人： Michael Armacost ,  Richard A. Conti ,  Jeffrey P. Gambino ,  Jeremy K. Stephens

    IPC分类号： H01L214763

    CPC分类号： H01L21/76897 ,  H01L21/31144 ,  H01L27/10873 ,  H01L27/10894

    摘要： A method of forming a semiconductor structure may include forming a semiconductor substrate having an array region and a support region, forming a semiconductor substrate and a gate stack over the support region of the substrate and applying a critical mask over the support region and the array region. The critical mask may have a first opening at an area corresponding to the array region and a second opening at an area corresponding to the support region. Contact holes may be formed in a glass layer at areas corresponding to the first and second opening. After removing the critical mask, a first blockout mask may be applied over the array region and a first conductive type dopant may be added to exposed polysilicon corresponding to openings of the blockout mask or gate contacts may be formed.

    摘要翻译： 形成半导体结构的方法可以包括形成具有阵列区域和支撑区域的半导体衬底，在衬底的支撑区域上形成半导体衬底和栅叠层，并在衬底区域和阵列区域上施加临界掩模 。 临界掩模可以在对应于阵列区域的区域处具有第一开口，并且在对应于支撑区域的区域处具有第二开口。 可以在对应于第一和第二开口的区域的玻璃层中形成接触孔。 在去除临界掩模之后，可以在阵列区域上施加第一堵塞掩模，并且可以形成第一导电型掺杂剂，以对应于封闭掩模的开口或栅极触点形成对应于暴露的多晶硅。

    Method for reducing stress in the metallization of an integrated circuit
    10.
    发明授权
    Method for reducing stress in the metallization of an integrated circuit 失效
    降低集成电路金属化应力的方法

    公开(公告)号：US5939335A

    公开(公告)日：1999-08-17

    申请号：US3107

    申请日：1998-01-06

    申请人： Kenneth C. Arndt ,  Richard A. Conti ,  David M. Dobuzinsky ,  Laertis Economikos ,  Jeffrey P. Gambino ,  Peter D. Hoh ,  Chandrasekhar Narayan

    发明人： Kenneth C. Arndt ,  Richard A. Conti ,  David M. Dobuzinsky ,  Laertis Economikos ,  Jeffrey P. Gambino ,  Peter D. Hoh ,  Chandrasekhar Narayan

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/336

    CPC分类号： H01L21/76804 ,  H01L21/32136 ,  H01L21/76835 ,  H01L21/76885

    摘要： The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.

    摘要翻译： 通过使与金属图案化方法（例如反应离子蚀刻（RIE）和镶嵌技术）一起制造的集成电路的电介质中通常感应的应力可以通过将与形成为集成电路的一部分的特征相关联的下角 在施加外部（即钝化）层之前，例如，互连）。 关于通过金属RIE工艺形成的金属线的形成，可以使用包括产生垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤的两步金属蚀刻工艺来实现这种角圆化 或者沿着垂直侧壁的下部产生锥形间隔物。 这导致圆角的底角，其改善了上覆电介质的台阶覆盖，从而消除了裂纹的可能性。 对于由大马士革图案化的金属线，可以使用包括产生垂直侧壁的第一步骤的两步沟槽蚀刻工艺，以及沿着垂直侧壁的下部产生锥形侧壁的第二步骤来实现这种角落圆化。